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AR# 32767

SPI-4.2 Lite v5.1, v5.1 Rev1 and v5.1 Rev2 - Release Notes and Known Issues for ISE 11.2, 11.3, 11.4 and 11.5 software


This Release Notes and Known Issues Answer Record is for the SPI-4.2 (POS-PHY L4) Lite v5.1 Core, released in ISE Design Suite 11.2, the SPI-4.2 (POS-PHY L4) Lite v5.1 Rev 1 Core, released in (Xilinx Answer 33455) for use in ISE Design Suite 11.3, and the SPI-4.2 (POS-PHY L4) Lite v5.1 Rev2 Core, release in ISE Design Suite 11.5, and contains the and contains the following information:
  • New Features
  • Bug Fixes
  • General Information
  • Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide:


Important Note: There is a v5.1 Rev1 patch available in (Xilinx Answer 33455). This patch is required to use the core in ISE 11.3/11.4 software with Spartan-6 FPGA.The fixes in this patch are also included in the v5.1 Rev2 Core.

New Features in v5.1

- ISE 11.2 software support

- Virtex-6 and Spartan-6 FPGA support

New Features in v5.1 Rev1

- ISE 11.3 software support

- (Xilinx Answer 33523) Support for Virtex-6 HXT and Virtex-6 -1L devices

New Features in v5.1 Rev2

-ISE 11.5 software support

Bug Fixes in v5.1

- None

Bug Fixes in v5.1 Rev1
(Xilinx Answer 33455) Map Error in Spartan-6 FPGA using 11.3 software: "ERROR:LIT:554 - OBUFTDS symbol..."

- Version fixed: v5.1 Rev 1

- CR 529067

Bug Fixes in v5.1 Rev2

(Xilinx Answer 34156) Virtex-6 FPGA core should not be used in production due to potential BRAM memory collision

General Information

Virtex-6 FPGA CXT devices are supported with the following performance:

-1 speed grade: up to 400 Mb/s (requires UCF file modification to add multi-cycle timing constraint for reset path).

See (Xilinx Answer 32920) for details on how to modify the UCF file.

(Xilinx Answer 20430) What is the power consumption of SPI-4.2 Lite Core?

(Xilinx Answer 20017) Which I/O Standards are supported for SPI-4.2 Core?

Multiple Cores: If you are using multiple SPI-4.2 Cores in a single device, see the Multiple Core Instantiation section under the Special Design Consideration chapter of the SPI-4.2 Lite User Guide. It is important to generate multiple cores with unique component names for each instance regardless of core configuration.

Known Issues in v5.1 and v5.1 Rev1

(Xilinx Answer 34156) Virtex-6 FPGA core should not be used in production due to potential BRAM memory collision

(Xilinx Answer 32922) Virtex-6 FPGA design returns "ERROR:Place:418 - Failed to execute IOB Placement" in Map (fixed in 11.4)

Known Issues in v5.1, v5.1 Rev1 and v5.1 Rev2

Constraints and Implementation Issues

- DDR mode is not supported in Banks 0 and 2 (top and bottom) in the Spartan-6 LX16 ES device. This only applies to "ES" devices and is fixed in Production Silicon.

Please see the Silicon Spartan-6 FPGA LX16 CES Errata for further information:


(Xilinx Answer 34562) MMCM Mult values outside of allowable range in Virtex-6

(Xilinx Answer 32920) Virtex-6 FPGA design might fail timing in PAR

(Xilinx Answer 22009) When implementing an SPI-4.2 Lite design through NGDBuild, several "INFO" and "WARNING" messages appear

(Xilinx Answer 21998) When implementing an SPI-4.2 Lite design through MAP, several "WARNING" messages appear

(Xilinx Answer 21999) When implementing an SPI-4.2 Lite design through BitGen, several "WARNING" messages appear

(Xilinx Answer 22011) There are missing example constraints in the UCF file

(Xilinx Answer 19999) "ERROR:BitGen:169 - This design contains one or more evaluation cores for which bitstream generation is not supported"

General Simulation Issues

(Xilinx Answer 34568) MMCM may not lock causing a failure in simulation using VCS

(Xilinx Answer 21319) TDat Error: Data mismatch error in timing simulation

(Xilinx Answer 22001) Design example results in warnings for source segmenting packets

(Xilinx Answer 21350) Demo testbench results in RDat Protocol violation warnings

(Xilinx Answer 21322) Timing simulation errors: SETUP, HOLD, RECOVERY violations

(Xilinx Answer 22026) Simulating SPI-4.2 Lite design results in "Error: /X_ODDR HOLD Low VIOLATION ON D1 WITH RESPECT TO C;"

Hardware Issues

(Xilinx Answer 20022) When fixed static alignment is used, it is necessary to determine the best IOBDELAY (ISERDES) value or the best DCM setting (PHASE SHIFT) to ensure that the target system contains the maximum system margin and performs across voltage, temperature, and process (multiple chips) variations.

Known Issues in v5.1 Rev2 (do not apply to v5.1 and v5.1 Rev1)

(Xilinx Answer 34252) Virtex-6 BRAM resource utilization in 11.5 Datasheet is not accurate

Revision History

06/24/2009 - Initial Release

09/16/2009 - Updated for v5.1 Rev1 patch and ISE 11.3 software

01/19/2010 - Added AR34156

03/03/2010 - Updated for Rev2

AR# 32767
Date 05/19/2012
Status Archive
Type Known Issues