AR# 32822

11.2 Virtex-6 MAP - "ERROR:Place:1164 - The clock source component ..."


I am receiving the following error related to MMCM connectivity during MAP:

ERROR:Place:1164 - The clock source component "DDR2SODIMMGen.DDR2/DDRBkg/u_mem_intfc/phy_top0/u_phy_read/mb_rdclk_gen_inst.u_phy_rdclk_gen/
u_mmcm_clk_base" and a load component
gen_ck_cpt[2].u_oserdes_cpt" have been constrained or locked on two locations that are too far from each other, which cause the clock signal unroutable.

My design appears to be fine.

Is this error correct?


There are some known cases where a check of the validity of MMCM placement has resulted in a false positive. 

For ISE version 11.2, an environment variable is being provided to bypass the error and continue processing.

This will provide a work-around for false positives for this error, and also to allow examination of the placed design in FPGA Editor in the case of a valid error. 

If the router is able to successfully route the design after the error is bypassed, then the error can be considered to have been false. 

Two cases of false errors are under investigation for a fix in ISE version 11.3.

To disable the Place:1164 error use the following commands:


For general information about setting ISE environment variables, see (Xilinx Answer 11630).

AR# 32822
Date 09/11/2014
Status Active
Type General Article
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