The difference is that Virtex-4 BUFR circuits (BUFIO driving BUFR in series) are automatically retargeted for Virtex-5 (BUFIO and BUFR in parallel and both driven by IO logic). It is Xilinx policy to only retarget across one architecture generation and so a Virtex-4 BUFR circuit is not retargeted for Virtex-6 and will not work. It is necessary to change the input design to correct the BUFR circuit.
| AR# 32825 | |
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| Date | 12/15/2012 |
| Status | Active |
| Type | General Article |
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