UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptable. Intelligent.
  2. Support
  3. AR# 32825: 11.2 Virtex-6 Route - Virtex-4 BUFR circuits are not retargeted to Virtex-6

AR# 32825

11.2 Virtex-6 Route - Virtex-4 BUFR circuits are not retargeted to Virtex-6

Description


My design contains a BUFR circuit that worked fine in Virtex-4 and Virtex-5, but it no longer works in Virtex-6.

What is different between a Virtex-5 and Virtex-6 that causes the BUFR circuit to no longer work?

Solution

The difference is that Virtex-4 BUFR circuits (BUFIO driving BUFR in series) are automatically retargeted for Virtex-5 (BUFIO and BUFR in parallel and both driven by IO logic). It is Xilinx policy to only retarget across one architecture generation and so a Virtex-4 BUFR circuit is not retargeted for Virtex-6 and will not work. It is necessary to change the input design to correct the BUFR circuit.

AR# 32825
Date 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
Tools
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • More
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • Less
Page Bookmarked