When retargeting a Virtex-4 design to Virtex-5, I receive the following error in timing simulation. Why?
Attribute Syntax Error : The Attribute CLKOUT0_DIVIDE on X_PLL_ADV instance tb_top.uut.PMCD_inst is set to 1 when attribute PLL_PMCD_MODE is set to TRUE. Legal values for this attribute is 8 when PLL in PMCD MODE.
This is an issue with retargeting from Virtex-4 FPGA to Virtex-5 FPGA with PMCD.
CLKOUT0 output is the divided 8 output for PMCD mode. Since simulation model does not know whether the output pin is used or left open, the attribute value of 8 will be checked for PMCD mode.
When retargeting, the tools need to automatically set the attributes CLKOUT0_DIVIDE to 8, CLKOUT1_DIVIDE to 4, CLKOUT2_DIVIDE to 2 and CLKOUT3_DIVIDE to 1 when attribute PLL_PMCD_MODE value is "TRUE".
This does not happen in 11.1 and 11.2, causing this error.
To work around this problem, you should set these attributes manually.
This issue is fixed in 11.3. The tools take care of retargeting.