The SPI-4.2 Core netlist generated by CORE Generator for Virtex-6 designs sets the HIGH_PERFORMANCE_MODE attribute on the IODELAYE1 elements to "TRUE". If targeting a performance of less than 700 Mbps, you can optionally change this attribute to "FALSE" in the UCF file. This will allow the IODELAY to consume less power.
To implement this optional change, the following must be added to the UCF file with correct instance path for the particular design:
INST "pl4_snk_clk0/rdclk_idel" HIGH_PERFORMANCE_MODE = "FALSE" ;
INST "<sink_core_instance_name>/U0/io0/*dpa2/dpa_top0/*DATAPAIR*/MASTER_DELAY" HIGH_PERFORMANCE_MODE = "FALSE" ;
INST "<sink_core_instance_name>/U0/io0/*dpa2/dpa_top0/*DATAPAIR*/SLAVE_DELAY" HIGH_PERFORMANCE_MODE = "FALSE" ;
INST "<sink_core_instance_name>/U0/io0/*dpa2/dpa_top0/*CTLPAIR*/SLAVE_DELAY" HIGH_PERFORMANCE_MODE = "FALSE" ;
INST "<sink_core_instance_name>/U0/io0/*dpa2/dpa_top0/*CTLPAIR*/MASTER_DELAY" HIGH_PERFORMANCE_MODE = "FALSE " ;
Revision History
06/24/2009 - Initial Release
| AR# 32917 | |
|---|---|
| Date | 12/15/2012 |
| Status | Active |
| Type | General Article |