AR# 32927
|XST - What is new in XST for Virtex-6 and Spartan-6 devices?
Description
What is new in XST for Virtex-6 and Spartan-6 devices?
Solution
In ISE Design Suite 11.2, XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families.
The new parser brings a lot of improvements to the XILINX Synthesis solution.
- Significantly enlarges VHDL/Verilog language coverage, including a great support for complex data structures such as records, multi-dimensional arrays, array of records, etc.
- Allows greater flexibility in design coding.
- Significantly reduces runtime and memory usage for processing of various HDL constructs.
- Processing of complex if, then, else, and case statements.
- Functions and generics calculation.
- Structural designs processing.
However, several constructs supported in the XST Standard version for older FPGA families (such as Virtex-5 and Spartan-3) are not VHDL/Verilog LRM compliant.
Some of them are rejected by the new parser and some of them are interpreted differently.
Such situations will require some VHDL/Verilog code changes to successfully process the design using the new parser.
In addition, several naming conventions were improved in XST for Virtex-6 and Spartan-6 families.
The names are more clear and predictable.
However, these changes might have an impact on existing UCF files and require some modification.
The goal of this solution record is to provide the list of changes in XST for Virtex-6 and Spartan-6 devices compared to XST Standard, which will require some designs adaptation when migrating designs to Virtex-6 and Spartan-6.
1) List of HDL constructs that need to be reworked before re-targeting the code for Virtex-6 and Spartan-6 devices.
| Topic | Message in XST | AR Number |
|---|---|---|
| Signal and Component Have the Same Name in a Scope | HDLCompiler:40 | (Xilinx Answer 32971) |
| Library and Component Have the Same Name in a Scope | HDLCompiler:40 | (Xilinx Answer 32993) |
| Instance and Component Have the Same Name in a Scope | HDLCompiler:40 | (Xilinx Answer 32997) |
| Signal and Process Label Have the Same Name in a Scope | HDLCompiler:56 | (Xilinx Answer 32998) |
| translate_off and translate_on Directives with Different Keywords | HDLCompiler:940 | (Xilinx Answer 32974) |
| Size Mismatch in Assignment | HDLCompiler:410 | (Xilinx Answer 32975) |
| Direct instantiation without Using Expanded Name | HDLCompiler:69 | (Xilinx Answer 32976) |
| Multi-Source in FSM Description | HDLCompiler:637 | (Xilinx Answer 32979) |
| Constant Declaration Depends on the Signal Initialized with another Constant | HDLCompiler:545 | (Xilinx Answer 32980) |
| Entity and Component Ports have Different Types | HDLCompiler:377 | (Xilinx Answer 32981) |
| Support of the last_value Predefined Attribute | HDLCompiler:236 | (Xilinx Answer 32982) |
| Multiple Declarations via Multiple use Clauses | HDLCompiler:607 | (Xilinx Answer 32983) |
| Constant Declared and Used in the Procedure Interface List | HDLCompiler:16 | (Xilinx Answer 32984) |
| Generic/Parameter Values Redefined in Command Line | HDLCompiler:852 | (Xilinx Answer 33031) |
2) HDL Constructs: Interpretation changes
| Topic | Message in XST | AR Number |
|---|---|---|
| Don't Care Values | No Warning/Error | (Xilinx Answer 33034) |
| Compare Operation with Operands Having Different Sizes | Xst:647 | (Xilinx Answer 33037) |
| Default Value of a Non-Initialized Signal of Type Integer or Float | HDLCompiler:871 | (Xilinx Answer 32985) |
| Location of Synthesis Metacomments in Verilog Files | HDLCompiler:924 | (Xilinx Answer 33038) |
| Elaborate command and Check Syntax Process | No Warning/Error | (Xilinx Answer 32986) |
3) New Naming Conventions
Linked Answer Records
Associated Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 39395 | 12.3 XST - "ERROR:Xst:2750 - line 1: Bad project format. Valid format is '[library_name] file_name'" | N/A | N/A |
| AR# 32927 | |
|---|---|
| Date | 03/23/2015 |
| Status | Active |
| Type | General Article |
| Tools | |