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AR# 32930

MIG v3.1, Virtex-6 DDR3 - Changes required to simulation testbench (sim_tb_top.v) to skip calibration and avoid memory overflow errors


When running the default MIG output simulation, calibration takes a very long time to complete and memory overflow errors might occur.

When a memory overflow occurs, ModelSim will generate an error similar to the following:

# sim_tb_top.comp_inst.mem_8_4.gen_mem[1].u_comp_ddr3.memory_write: at time 40733688.0 ps ERROR: Memory overflow. Write to Address 00083e with Data xxxxxxxx001f0041 will be lost.

# You must increase the MEM_BITS parameter or define MAX_MEM.

Init_done does not ever assert.


To work around these long simulation times, the calibration algorithm can be abbreviated by changing parameters in the sim_tb_top.v module.

By default the simulation parameters used to control the calibration sequence are set as follows:

parameter SIM_INIT_OPTION = "NONE";
parameter SIM_CAL_OPTION = "NONE";

To abbreviate the calibration sequence, change these parameter setting in the 'example_design/sim/sim_tb_top.v" or 'user_design/sim/sim_tb_top.v' module:

parameter SIM_CAL_OPTION = "FAST_CAL";

If a memory overflow error occurs, the end address location used in memory can be decreased.

The end address locations are set in the same sim_tb_top.v module as follows:

parameter END_ADDRESS = 32'h00ffffff;
parameter PRBS_EADDR_MASK_POS = 32'hff000000;

To avoid memory overflows, change these parameters as follows:

parameter END_ADDRESS = 32'h000003ff;
parameter PRBS_EADDR_MASK_POS = 32'hfffffc00;

These parameters will be changed in the testbench to the above values in MIG 3.2.
AR# 32930
Date 08/25/2014
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
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