Xilinx leverages the latest encryption methodology as specified in Verilog LRM - IEEE Standard 1364-2005.
Simulation models for the Hard-IP, such as the PowerPC processor, MGT, and PCIe, leverage this technology.
For more information, refer to the following:
Note: Because SecureIP is a Verilog standard, ModelSim and Questa require a Verilog license.
If you do not have a Verilog license, see (Xilinx Answer 33118).
Xilinx provides a tool called CompXlib which compiles Xilinx libraries (including SecureIP libraries).
For more information, see the Command Line Tools User Guide at: http://www.xilinx.com/support/documentation/dt_ise.htm.
CompXlib sets up the libraries automatically and the "Modelsim.ini" file is edited accordingly.
Once the libraries are compiled using CompXlib, there are no additional changes needed for the "Modelsim.ini" file.
Additional switch needed in VSIM command
The only additional switch that is needed when running ModelSim simulation after compiling Xilinx libraries is the -L switch that points to the SecureIP library.
If using Project Navigator, to add the "-L secureip" option to the vsim command in the ".fdo" file, add "-L secureip" to the "Other VSIM Command Line Option" field in the advanced Simulation properties.
If there are issues running SecureIP simulation, open a WebCase with Xilinx Technical Support at: