AR# 32937


VCS - How do I simulate SecureIP with VCS?


How do I simulate SecureIP with VCS?


Xilinx leverages the latest encryption methodology as specified in Verilog LRM - IEEE Std 1364-2005. Simulation models for the Hard-IP such as the PowerPC processor, MGT, and PCIe leverage this technology.

For more information, please refer to the following:

Starting with 11.1, all hardIP blocks are encrypted using SecureIP. For supported version of VCS, please refer to the Synthesis and Simulation Guide.

Using Library Source Files With Compile Time Options

Depending on the makeup of the design (Xilinx instantiated primitives or CORE Generator softwarecomponents), for Register Transfer Level (RTL) simulation, specify the following at the command line:

vcs -f $XILINX/secureip/vcs/vcs_secureip_cell.list.f \

-y $XILINX/verilog/src/unisims -y $XILINX/verilog/src/xilinxcorelib \

+incdir+$XILINX/verilog/src +libext+.v $XILINX/verilog/src/glbl.v \

-lca-Mupdate -R <testfixture>.v <design>.v

NOTE:Do not use the -y switch to point to the SecureIP library locations. This approach can lead to compilation errors/hangs. Rather, make use of the -f switch as recommended above.

Similarly, for timing simulation the SIMPRIM-based libraries are used. Specify the following at the command line:

vcs +compsdf -y $XILINX/verilog/src/simprims $XILINX/verilog/src/glbl.v \

-f $XILINX/secureip/vcs/vcs_secureip_cell.list.f \

-lca+libext+.v -Mupdate -R <testfixture>.v time_sim.v

If you are using the system verilog switch with SecureIP, refer to (Xilinx Answer 32821) />
If there are issues running SecureIP simulation, open a WebCase with Xilinx Technical Support at:

NOTE:Adding the "-lca" switch to a VCS/VCS-MX command line enables a suite of "limited customer availability" features. The exact set of features differ from release to release, but is documented in the "LCA Features" portion of "vcs -doc".Note that VCS or VCS-MX also issues a compile-time warning message as a reminder that you have used this switch.

Synopsys has a conservative process whereby features are introduced into Xilinx products in phases.This conservative procedure is rigidly followed to create a more stable and robust environment for a large user base.

Initially, new features will appear in the tool unpublicized as R&D works directly with a few users who are requesting a new feature.

In the next phase (Beta), the field-support organization introduces the new feature into a variety of other users and provides important feedback.

In a subsequent release, when enough confidence has been obtained, Synopsys will bring the feature into "limited customer availability".At this time, anyone can begin using the feature because it appears in the documentation as mentioned above. Users must add the "-lca" switch to enable this new feature.

With additional confidence, in an ensuing tool release, Synopsys will move the feature into full production where the "-lca" switch is no longer be needed.

Please understand that some features are addressed to a subset of the user-base, and it might take longer to achieve the confidence to move between these phases. By providing feedback on new releases and new features, users can take an active part to accelerate this process.

AR# 32937
Date 02/26/2013
Status Active
Type General Article
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