The SPI-4.2 Core has certain "static configuration signals" that control various aspects of the core functionality.
Can these values be changed in-circuit?
Users of the core can change the following static settings for the SPI-4.2 Core during reset assertion (but NOT during regular operation, or on the fly):
The following steps to perform these changes are recommended. These steps have been verified in functional and timing simulations with the SPI-4.2 v9.3 Core, and information has been added to that User Guide.
1. Disable the sink and source core (SnkEn and SrcEn signals).
2. Assert core reset (Reset_n = 0).
3. Change the desired static configuration signals.
4. Deassert reset (Reset_n=1).
5. Wait at least 10 clock cycles of RDClkDiv_GP for the sink static configuration signals to settle, and 10 clock cycles of SysClkDiv_GP for the source static configuration signals to settle and propagate to the logic.
6. Enable the core and wait for the core to achieve synchronization, then continue normal operation.
06/24/2009 - Initial Release
09/16/2009 - Updated verification info