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AR# 32949

11.1 Timing - Negative "Delay" values for one of TIG constraints


In my timing report, there are negative "Delay" values for my TIG constraint. The path has a timing ignore constraint.

Why does it still show up in an error only report, and why is it showing as a negative?


When a TIG is placed on a path, then the path is trully ignored by the tools for timing-driven placement and packing.

The tools will presume that the source and destination clocks are phase aligned and calculate "Delay". "Delay" is different than "Slack". Negative "Slack" indicates a timing violation, whereas negative "Delay" is just indicating that the math produced a negative value. When "Delay" is reported a requirement is not used.

The tools report the negative value, but it is "Delay" not "Slack", and it can be safely ignored.


Timing constraint: PATH "TS_my_timespec1" TIG;

4 paths analyzed, 4 endpoints analyzed, 0 failing endpoints

0 timing errors detected. (0 setup errors, 0 hold errors)



Timing constraint: PATH "TS_my_timespec2" TIG;

48 paths analyzed, 48 endpoints analyzed, 0 failing endpoints

0 timing errors detected. (0 setup errors, 0 hold errors)


Delay: -5.021ns (data path - clock path skew + uncertainty)

Source: MY_RAM (RAM)

Destination: MY_FF (FF)

Data Path Delay: 1.914ns (Levels of Logic = 1)

Clock Path Skew: 7.083ns (9.819 - 2.736)

Source Clock: MY_CLK1 rising

Destination Clock: MY_CLK2 rising

Clock Uncertainty: 0.148ns

Clock Uncertainty: 0.148ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE

Total System Jitter (TSJ): 0.070ns

Discrete Jitter (DJ): 0.083ns

Phase Error (PE): 0.092ns

Maximum Data Path: MY_RAM to MY_FF

Location Delay type Delay(ns) Physical Resource

Logical Resource(s)

------------------------------------------------- -------------------



SLICE_X1Y100.A6 net (fanout=1) 0.524 MY_NET



------------------------------------------------- ---------------------------

Total 1.914ns (1.390ns logic, 0.524ns route)

AR# 32949
Date 12/15/2012
Status Active
Type General Article
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