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AR# 32975

ISE Design Suite 11.2 XST - " ERROR:HDLCompiler:410 - ".vhd" Line xx: Expression has x elements; expected y"

Description

I receive the following error when I target Virtex-6/Spartan-6 devices, but the same code passes with a warning when targeting older devices. 

How do I resolves this? 

ERROR:HDLCompiler:410 - "<file>.vhd" Line xx: Expression has x elements ; expected y 

Example code: 

 

library ieee; 

use ieee.std_logic_1164.all; 

use ieee.numeric_std.all; 

 

entity ex_0006 is 

port(a,b : in unsigned (7 downto 0); 

res : out unsigned (8 downto 0)); 

end ex_0006; 

 

architecture beh of ex_0006 is 

begin 

 

res <= a + b; -- Note: Error points here 

 

end beh;

Solution

The above code is not VHDL LRM compliant.

To resolve the error, use the resize function from the numeric_std package to align the left and right side of assignment. 

 

library ieee; 

use ieee.std_logic_1164.all; 

use ieee.numeric_std.all; 

entity ex_0006 is 

port(a,b : in unsigned (7 downto 0); 

res : out unsigned (8 downto 0)); 

end ex_0006; 

 

architecture beh of ex_0006 is 

begin 

 

res <= resize(a,9) + resize(b,9); -- Note: Error points here 

 

end beh; 

 

ISE Design Suite 11.2 XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families.


For more information on this change, please refer to (Xilinx Answer 32927)

AR# 32975
Date Created 06/23/2009
Last Updated 02/27/2015
Status Active
Type General Article
Tools
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • More
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13.1
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