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AR# 32981

11.2 XST - "ERROR:HDLCompiler:377 - ".vhd" Line xx: Entity port in_port does not match with type std_logic_vector of component port"

Description

The following error occurs in XST when I target Virtex-6 or Spartan-6 devices, but I do not have any issues when I target older devices. Why?

ERROR:HDLCompiler:377 - "<file>.vhd" Line xx: Entity port in_port does not match with type std_logic_vector of component port

"<file>.vhd" Line xx: in_port is declared here

Example code:

library ieee;

use ieee.std_logic_1164.all;

entity subb_0014 is

port(in_port : in bit_vector(3 downto 0);

out_port: out bit_vector(3 downto 0));

end subb_0014;

architecture beh of subb_0014 is

begin

out_port <= in_port;

end;

------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

entity ex_0014 is

port(in_port : in std_logic_vector(3 downto 0);

out_port: out std_logic_vector(3 downto 0));

end ex_0014;

architecture beh of ex_0014 is

component subb_0014 is

port(in_port : in std_logic_vector(3 downto 0);

out_port: out std_logic_vector(3 downto 0));

end component;

begin

inst : subb_0014 port map(in_port => in_port, out_port=>out_port);

end;

Solution

In the example above, the subb_0014 sub block has 2 ports of type bit_vector. The component subb_0014 declared in the ex_0014 has 2 ports of a different type: std_logic_vector. This is not a VHDL LRM compliant code.

To solve this issue, align the entity and component port types.

library ieee;

use ieee.std_logic_1164.all;

entity subb_0014 is

port(in_port : in std_logic_vector(3 downto 0); -- Note: Info points here

out_port: out std_logic_vector(3 downto 0)); -- Note: Info points here

end subb_0014;

architecture beh of subb_0014 is

begin

out_port <= in_port;

end;

------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

entity ex_0014 is

port(in_port : in std_logic_vector(3 downto 0);

out_port: out std_logic_vector(3 downto 0));

end ex_0014;

architecture beh of ex_0014 is

component subb_0014 is

port(in_port : in std_logic_vector(3 downto 0); -- Note: Error points here

out_port: out std_logic_vector(3 downto 0)); -- Note: Error points here

end component;

begin

inst : subb_0014 port map(in_port => in_port, out_port=>out_port);

end;

In 11.2, XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families. For more information on this change, see(Xilinx Answer 32927).

AR# 32981
Date Created 06/23/2009
Last Updated 12/15/2012
Status Active
Type General Article