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AR# 32986

11.2 XST - Unable to use elaborate command to pre-compile VHDL and Verilog files when targeting Virtex-6 or Spartan-6 for my design

Description

I am unable to use elaborate command in XST to pre-compile VHDL and Verilog files when targeting Virtex-6 or Spartan-6 devices. However, this command works fine for older devices. Why?

Solution

The goal of the elaborate command is to perform a syntax check (HDL Parsing) of the design.

In 11.2, XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families. For more information on this change, see (Xilinx Answer 32927).

In XST for Virtex-6 and Spartan-6 families, this command is obsolete and replaced by the run command used with compileonly switch and value yes. The run command is used by ISE Project Navigator when Check Syntax process is launched.

Following is a fragment of an XST script file generated by Project Navigator for Check Syntax process:

run -compileonly yes

-p xc6slx4-2-die

-top A_0000

-opt_mode Speed

-opt_level 1

-power NO

-iuc NO

-lso A_0000.lso

-keep_hierarchy NO

-netlist_hierarchy as_optimized

AR# 32986
Date Created 06/23/2009
Last Updated 12/15/2012
Status Active
Type General Article