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AR# 33018

Spartan-6 Clocking - ISE 11.2 PLL attributes set incorrectly, resulting in increased jitter calculations


Spartan-6 FPGA PLL jitter calculations might not be set correctly in the ISE 11.2 software tools. This issue has been fixed in ISE 11.3 software and later versions.


For the PLL in Spartan-6 FPGA, there are internal attribute settings which are automatically calculated based on routing rules for the input clock ports. Some of these are set incorrectly in the ISE 11.2 software which results in incorrect jitter calculations in the timing tools.

The issue has been fixed in ISE 11.3 software and later versions. To work past this issue, all Spartan-6 FPGA designs should be reimplemented in ISE 11.3 software or later.
AR# 33018
Date Created 06/22/2009
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • ISE Design Suite - 11.2
  • PLL Module