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AR# 33025

11.2 Spartan-6 Place - ERROR:Place:1136 - This design contains a global buffer instance...


My design fails with the following error. What is meant by "non-clock source pins"? What restriction is causing my design to fail?

ERROR:Place:1136 - This design contains a global buffer instance,

<CLK_16M384_BUFG>, driving the net, <CLK_16M384>, that is driving the

following (first 30) non-clock source pins.


This is not a recommended design practice in Spartan-6 due to limitations in

the global routing that may cause excessive delay, skew or unroutable

situations. It is recommended to only use a BUFG resource to drive clock

loads. If you wish to override this recommendation, you may use the

CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote

this message to a WARNING and allow your design to continue.



The phrase "non-clock source pins" should be "non-clock load pins". This will be corrected in ISE version 11.3.

The routing restriction in question leading to this error is that for Spartan-6 devices, only the eight BUFGs from the "upper" column of BUFG sites can drive non-clock loads. The Spartan-6 clock placer is currently not designed to recognize clock nets with non-clock load pins and constrain them to an appropriate BUFG site. This problem can be worked around by manually constraining the BUFG driver to an upper row site and using the CLOCK_DEDICATED_ROUTE constraint detailed in the error message to downgrade the error to a warning. The valid site names for the upper column of BUFG sites can be identified by examining the available sites in FPGA Editor. The following commands can be used to zoom into the BUFG sites:

select site BUFG*

zoom selection

Choose an available BUFG site from the upper group of eight and add a LOC constraint to the UCF file. For example:

INST "bufg_symbol_name" LOC = BUFGMUX_X3Y8;
AR# 33025
Date 09/09/2010
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • ISE Design Suite - 11.2