AR# 33106

Virtex-6 FPGA Integrated Block Wrapper v1.3 for PCI Express - ModelSim simulation does not show all signals in hierarchy


Known Issue: v1.3, v1.2, v1.1

After using the "" file to run the example design simulation, the design hierarchy in ModelSim does not show all the signals and ports in the core when viewing in the Objects window.


The vsim command line requires an additional switch (-voptargs="+acc") to keep signals from being optimized. The vsim command-line in should be changed as follows:

vsim -voptargs="+acc" +notimingchecks +TESTNAME=sample_smoke_test0 -L work -L secureip -L unisims_ver \

work.board glbl +dump_all

Revision History

09/16/2009 - Updated for ISE Design Suite 11.3 and wrapper v1.3

07/08/2009 - Initial Release
AR# 33106
Date 08/06/2010
Status Active
Type ??????