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AR# 33152

PlanAhead 11.2 - DRC errors on clock placement for Spartan-3 derivatives.


Keywords: DCM, BUFG, I/O, input

When I run DRC on my Spartan-3/3E/3A/3ADSP design, I get errors on the placement of my clocking related instances. I have checked the Spartan-3 Family User Guide and my placement constraints are correct. Can I ignore these errors?


If your design meets all documented requirements, you can safely ignore these errors. This will be fixed in an upcoming PlanAhead release.

AR# 33152
Date 07/20/2009
Status Active
Type General Article
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