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AR# 33157

10.1 EDK - NGDBuild 604: logical block '*\*_FIFO' with type 'trimode_mac_gmii_wrapper_sync_fifo_v5_0_3' could not be resolved

Description

Keywords: NGDBuild, 604, platgen, trimode, mac, fifo, sync, async

"ERROR:NgdBuild:604 - logical block 'TriMode_MAC_GMII/TriMode_MAC_GMII/I_RX0/I_RX_STATUS_FIFO' with type 'trimode_mac_gmii_wrapper_sync_fifo_v5_0_3' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'trimode_mac_gmii_wrapper_sync_fifo_v5_0_3' is not supported in target 'virtex4'."

This is a known issue with generatecore utility in EDK 10.1.03i, and happens because the CORE Generator JVM does not have adequate virtual memory.

This can be confirmed from the following messages in the synthesis report (*.srp) available in the <Project>\synthesis folder.

Release 10.1.03 - edk_generatecore $Revision: 1.1.2.1.4.14.4.11 $ (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
Error occurred during initialization of V
Could not reserve enough space for object hea
Could not create the Java virtual machine
ERROR:coreutil - Aborting CORE Generator execution!
Generated unit <trimode_mac_gmii_wrapper_sync_fifo_v5_0_1>.

Solution

The work-around for this issue is to generate the core from CORE Generator manually and copy it to the <Project>\implementation folder before running "Generate bitstream".

1. Close all Xilinx applications and set the environment variable XIL_COREUTIL_DEBUG_GENERATECORE to "true".

2. Ensure that EDK cygwin is in the environment variable PATH and the variables TEMP and TMP point to folders that have no spaces in them.

PATH = %XILINX_EDK%\cygwin\bin;%PATH%
TEMP = C:\Temp
TMP = C:\Temp

3. Open the XPS project, clean all the hardware and generate the netlist. The build will fail as it did earlier.

4. Open <Project>\synthesis\trimode_mac_gmii_xst_wrapper.srp file in a text editor and search for "edk_generatecore".

5. For each "edk_generatecore" run, you will see the options for the command line run.

Release 10.1.03 - edk_generatecore $Revision: 1.1.2.1.4.14.4.11 $ (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.

INFO:coreutil - Arguments passed to core generator:
#cell=trimode_mac_gmii_wrapper_sync_fifo_v5_0_1
#simName=com.xilinx.ip.sync_fifo_v5_0.sync_fifo_v5_0
#component=trimode_mac_gmii_wrapper_sync_fifo_v5_0_1
#targetArch=virtex4
#library=proc_common_v2_00_a
#package=coregen_comp_defs
#outputFile=trimode_mac_gmii_wrapper_sync_fifo_v5_0_1.edn
#outputDirectory=../implementation/
#-p
c_wr_ack_low=0
c_dcount_width=9
c_has_dcount=0
c_read_depth=64
c_has_rd_ack=1
c_memory_type=1
c_read_data_width=36
c_rd_err_low=0
c_enable_rlocs=0
c_wr_err_low=0
c_has_rd_err=0
c_rd_ack_low=0
c_write_data_width=36
c_ports_differ=0
c_has_wr_ack=0
c_has_wr_err=0
c_write_depth=64
#-attribute map_qvirtex_to=virtex
#-attribute map_qrvirtex_to=virtex
#-attribute map_virtexe_to=virtex
#-attribute map_qvirtex2_to=virtex2
#-attribute map_qrvirtex2_to=virtex2
#-attribute map_spartan2e_to=spartan2
#-attribute map_spartan3e_to=spartan3
#-attribute map_virtex5_to=virtex4
#-attribute map_spartan3a_to=spartan3
#-attribute map_spartan3an_to=spartan3
#-attribute map_spartan3adsp_to=spartan3

Executing: C:/Xilinx/10.1/ISE/java/nt/jre/bin/java -Xmx1048m -Xms10m -cp C:\Xilinx\10.1\EDK/hw/coregen/lib/coreutil.jar;C:\Xilinx\10.1\EDK/hw/coregen/lib/sim.jar;C:\Xilinx\10.1\EDK/hw/coregen/lib/xcc.jar;;C:/Xilinx/10.1/ISE/coregen/lib/coreutil.jar;C:/Xilinx/10.1/ISE/coregen/lib/sim.jar; C:/Xilinx/10.1/ISE/corege
n/lib/xcc.jar;;C:/Xilinx/10.1/ISE/coregen/ip/xilinx/dsp;C:/Xilinx/10.1/ISE/coregen/ip/xilinx/network; C:/Xilinx/10.1/ISE/coregen/ip/xilinx/other;C:/Xilinx/10.1/ISE/coregen/ip/xilinx/primary com.xilinx.sim.netlisters.NetlisterAPI -APIFile=C:/Temp/xil_8580_5trimode_mac_gmii_wrapper_sync_fifo_v5_0_1.opt

Arguments file C:/Temp/xil_8580_5trimode_mac_gmii_wrapper_sync_fifo_v5_0_1.opt
not deleted.

6. Copy this command to a temporary text document and modify the memory option -Xmx1024m to -Xmx512m.

C:/Xilinx/10.1/ISE/java/nt/jre/bin/java -Xmx512m -Xms10m -cp C:\Xilinx\10.1\EDK/hw/coregen/lib/coreutil.jar;C:\Xilinx\10.1\EDK/hw/coregen/lib/sim.jar;C:\Xilinx\10.1\EDK/hw/coregen/lib/xcc.jar;;C:/Xilinx/10.1/ISE/coregen/lib/coreutil.jar;C:/Xilinx/10.1/ISE/coregen/lib/sim.jar; C:/Xilinx/10.1/ISE/coregen/lib/xcc.jar;;C:/Xilinx/10.1/ISE/coregen/ip/xilinx/dsp;C:/Xilinx/10.1/ISE/coregen/ip/xilinx/network; C:/Xilinx/10.1/ISE/coregen/ip/xilinx/other;C:/Xilinx/10.1/ISE/coregen/ip/xilinx/primary com.xilinx.sim.netlisters.NetlisterAPI -APIFile=C:/Temp/xil_8580_5trimode_mac_gmii_wrapper_sync_fifo_v5_0_1.opt

7. Open a DOS command prompt and change the directory to <Project>\synthesis and run this command modified in step 6.

8. Repeat steps 4-7 for every failed instance of edk_generatecore.

9. Implement the design in XPS by selecting "Generate Bitstream" in the GUI.

For more information on CORE Generator JVM requirements, please refer to (Xilinx Answer 20708).

AR# 33157
Date Created 08/13/2009
Last Updated 08/17/2009
Status Active
Type General Article