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AR# 33209

11.x XST - "WARNING:Xst:2971 - This design infers one or more latches/registers with both an active asynchronous set and reset..."

Description

The following warning occurs in XST when I target a Virtex-6 FPGA design. How can I fix it?

In 11.2:

WARNING:Xst:2971 - This design infers one or more latches/registers with both an active asynchronous set and reset. In Virtex-6, this creates a sub-optimal circuit in area, power and performance. For optimal implementation, Xilinx highly recommends the following:

1. Remove either set or reset.

2. Make the function synchronous.

List of register instances with set and reset:

q in unit <ff_rtg_1>

In 11.3 and later:

WARNING:Xst:2971 - This design contains one or more registers or latches with an active asynchronous set and asynchronous reset. While this circuit can be built, it creates a sub-optimal implementation in terms of area, power and performance. For a more optimal implementation, Xilinx highly recommends one of the following:

1. Remove either the set or reset from all registers and latches if not needed for required functionality.

2. Modify the code in order to produce a synchronous set and/or reset (both is preferred).

3. Use the -async_to_sync option to transform the asynchronous set/reset to synchronous operation (timing simulation highly recommended when using this option).

For more details, please refer to: http://www.xilinx.com (search string "Virtex-6 asynchronous set/reset").

List of register instances with asynchronous set and reset:

q in unit <ff_rtg_1>

Solution

If you are experiencing this warning when targeting a Spartan-6 device, please refer to (Xilinx Answer 33210).

Virtex-6 FPGA

In Virtex-6 FPGA devices, the REV pin has been removed from flip-flops in order to reduce cost of the overall architecture. As a result, flip-flops no longer can natively implement both a set and reset signals. If registers with reset and set signals appear in the design, XST will automatically implement them using additional elements such as LUTs, Flip-Flops, and Latches.

Using Latches for Implementation

If a register description contains both asynchronous reset and asynchronous set signals, this register will be implemented using two registers, a LUT and a latch. In addition, XST will issue a warning message (WARNING:Xst:2971) indicating the presence of such situation in the design and list the corresponding registers.

Xilinx highly recommends the following:

- Avoid using unnecessary set and reset signals wherever possible in the design, and

- When necessary, use synchronous sets and reset signals.

Following these suggestions allows you to obtain better area, power, and performance results.

The table below shows the main cases when additional resources are required for register implementation.

.

Example 1: A register with a synchronous reset and an initialization value of 1

VHDL

.

Implementation

The implementation contains one FF with a synchronous reset and an initialization value of 0 (no additional logic required for its implementation).

XST LOG

Virtex-6: No message is issued.

NOTE: Similar implementation is obtained for a register with a synchronous set and an initialization value of 0.

Example 2: A register with a synchronous reset and an initialization value of 0

VHDL

.

Implementation

The implementation contains one FF with a synchronous set and an initialization value of 0 and one LUT2.

Implementation Schematic

.

XST LOG

Virtex-6: No message is issued.

NOTE: Similar implementation is obtained for a register with a synchronous set and an initialization value of 1.

Example 3: A register with an asynchronous reset and an initialization value of 1

VHDL

.

Implementation

The implementation contains one FF with an asynchronous reset and an initialization value of 1 (no additional logic required for its implementation).

XST LOG

Virtex-6: No message is issued.

NOTE: Similar implementation is obtained for a register with an asynchronous set and an initialization value of 0.

Example 4: A register with an asynchronous reset and an asynchronous set

VHDL

.

Implementation

The implementation contains two FFs, one LUT3 and one Latch.

Implementation Schematic

.

XST LOG

Virtex-6: WARNING:Xst:2971 is issued.

AR# 33209
Date Created 08/03/2009
Last Updated 12/21/2009
Status Active
Type General Article