AR# 3321


CPLD XC9500 Family - Is there a done pin for CPLDs?


KEYWORDS: reset, CPLD, 9500, done, verify

Is there a done pin for the XC9500 family devices? On FPGAs there is a DONE pin to indicate when the FPGA has a design loaded and

the chip is operational.


There is no DONE pin for the XC9500 family of devices. Upon power-up the device automatically configures itself and begins operation with no 'configured' pin.

If you are concerned whether the design was loaded properly, you may perform a JTAG Verify operation. This will read back the configuration registers of the CPLD and compare them to the JEDEC file and determine if the two differ.

AR# 3321
Date 12/15/2012
Status Active
Type General Article
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