KEYWORDS: reset, CPLD, 9500, done, verify
Is there a done pin for the XC9500 family devices? On FPGAs there is a DONE pin to indicate when the FPGA has a design loaded and
the chip is operational.
There is no DONE pin for the XC9500 family of devices. Upon power-up the device automatically configures itself and begins operation with no 'configured' pin.
If you are concerned whether the design was loaded properly, you may perform a JTAG Verify operation. This will read back the configuration registers of the CPLD and compare them to the JEDEC file and determine if the two differ.