UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33210

11.x XST - WARNING:Xst:2971 - This design infers one or more latches/registers with both an active asynchronous set and reset.

Description

Keywords : Virtex-6 asynchronous set/reset, Spartan-6 asynchronous set/reset, 2971, latches, registers, Virtex-6, Spartan-6

I get the following warning in XST when targeting Spartan-6 design. How can I fix it?

In 11.2:

WARNING:Xst:2971 - This design infers one or more latches/registers with both an active asynchronous set and reset. In Virtex6 this creates a sub-optimal circuit in area, power and performance. For optimal implementation Xilinx highly recommends the following

1) remove either set or reset.

2) make the function synchronous.

List of register instances with set and reset:

q in unit <ff_rtg_1>

In 11.3 and later:

WARNING:Xst:2971 - This design contains one or more registers or latches with an active asynchronous set and asynchronous reset. While this circuit can be built, it creates a sub-optimal implementation in terms of area, power and performance. For a more optimal implementation Xilinx highly recommends one of the following:

1) Remove either the set or reset from all registers and latches

if not needed for required functionality

2) Modify the code in order to produce a synchronous set and/or

reset (both is preferred)

3) Use the ?async_to_sync option to transform the asynchronous

set/reset to synchronous operation (timing simulation highly

recommended when using this option)

Please refer to http://www.xilinx.com search string ?Virtex-6

asynchronous set/reset? for more details.

List of register instances with asynchronous set and reset:

q in unit <ff_rtg_1>

Solution

If you are seeing this warning when targeting Virtex-6 Please refer (Xilinx Answer 33209)

In Spartan-6,

- The REV pin has been removed from flip-flops in order to reduce cost of the overall architecture. As a result, flip-flops no longer can natively implement both a set and reset signals.

- In addition, a register with a set or reset signal can have an initialization value of the same polarity only. For example, a flip-flop with an asynchronous reset can have an initialization value of 0.

If registers

- With reset and set signals and/or

- With reset or set signals have initialization values of the opposite polarity appear in the design, XST will automatically implement them using additional elements such as LUTs, Flip-Flops, and Latches.

Using Latches for Implementation

If a register description

- Contains both asynchronous reset and asynchronous set signals and/or

- Contains an asynchronous reset or set signal with an initialization value of the opposite polarity then this register will be implemented using a latch. In addition, XST will issue a warning (WARNING: Xst: 2970) message indicating the presence of such situations in the design and listing the corresponding registers.

Register Initialization

Many engineers use the inherent initialization of registers and latches in the FPGA via the Global Set/Reset (GSR) signal by explicitly or implicitly specifying initialization of an inferred register thus creating a more robust and sometimes smaller circuit.

In the following example the reg register is explicitly initialized with the value of ?1'.

.

With the earlier mentioned restrictions of the initialization polarity in Spartan-6, initialization must be more closely monitored to ensure it does not negatively impact area, power and performance. It is still recommended to initialize registers, however it is suggested to always match this initialization value with the described asynchronous/synchronous set or reset unless needed for design functionality. When a different initialization is needed from the set/reset value, then it is highly suggested to use synchronous set/resets whenever possible.

Particular attention must be paid when an initialization value is not explicitly specified in VHDL code. Even though, the initial value of a signal is not explicitly specified in VHDL code, it is still exist and depends on signal type. Several design cases are presented below.

Type: std_logic

The default value of std_logic type is equal to the left bound value of std_logic type definition, i.e. 'U' (Uninitialized). Taking into account that the ?U' value is meaningful for logic synthesis, XST ignores this value. In the following example the reg signal is not explicitly initialized:

.

As a consequence:

- No additional resources are required to implement this register and

- INIT property is not attached to this register.

Type: integer

The default value of integer type is equal to the left bound value of integer type definition (similar to std_logic type). However the final result differs from std_logic type as shown in the following example, where the reg signal has integer type:

.

In the above example the default value of the reg signal it is equal to 0. The fact that the reg register is reset to 7 and initialized to 0 requires the synthesis tool to use additional FPGA resources for its implementation.

If an initialized value of 0 is not necessary for functionality, the signal reg should be manually initialized to 7 to match the reset value specified in the associated process. If it is determined that an initialized value of 0 is needed, then it is suggested to change the asynchronous rst signal to be described synchronously. This allows to avoid using latches for its implementation.

Type: enumerated

State machines described using enumerated type is another case requiring your attention. The default value of enumerated type is equal to the left bound value of enumerated type definition (similar to std_logic and integer types). In the following example the default value of the next_state state register is not explicitly specified and therefore equal to s1:

.

As we can see then default value and the value forced by the asynchronous rst signal are different. You should follow the above suggestions in order to obtain the optimal implementation of your circuit.

Xilinx highly recommends

> To avoid using unnecessary set and resets signals wherever possible in the design and

> When necessary, use synchronous sets and resets signals

Following these suggestions will allow you to obtain better area, power, and performance results.

The table shows the main cases when additional resources are required for register implementation.
The table shows the main cases when additional resources are required for register implementation.
.

Example 1: A register with a synchronous reset and an initialization value of ?1'

VHDL

.

Implementation

The implementation contains one FF with an initialization value of ?0' and one LUT2

Implementation Schematic

.

XST LOG

Spartan-6: No message is issued.

Note

Similar implementation is obtained for a register with a synchronous set and an initialization value of ?0'.

Example 2: A register with a synchronous reset and an initialization value of ?0'

VHDL

.

Implementation

The implementation contains one FF with a synchronous set and an initialization value of ?0' and one LUT2

Implementation Schematic

.

XST LOG

Spartan-6: No message is issued.

Note

Similar implementation is obtained for a register with a synchronous set and an initialization value of ?1'.

Example 3: A register with an asynchronous reset and an initialization value of ?1'

VHDL

.

Implementation

The implementation contains two FFs, one LUT3 and one Latch

Implementation Schematic

.

XST LOG

Spartan-6: WARNING:Xst:2971 is issued.

Note

Similar implementation is obtained for a register with an asynchronous set and an initialization value of ?0'.

Example 4: A register with an asynchronous reset and an asynchronous set

VHDL

.

Implementation

The implementation contains two FFs, one LUT3 and one Latch.

Implementation Schematic

.

XST LOG

Spartan-6: WARNING:Xst:2971 is issued.

AR# 33210
Date Created 08/17/2009
Last Updated 12/20/2009
Status Active
Type General Article