We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33211

11.2 Virtex-4 MAP - Shift Register logic corrupted by Global Optimization algorithm


My design does not work in hardware and I have traced the problem area to a shift register. The problem is also dependent on the use of the -global_opt option of MAP. Is this a known problem?


There is a known problem that shift register logic can be occasionally corrupted by the Global Optimization algorithm.

This problem has been fixed for ISE revision 11.3.
AR# 33211
Date 12/15/2012
Status Active
Type General Article
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
Page Bookmarked