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AR# 33223

11 EDK - ERROR:PhysDesignRules:1690 - Incomplete PLL_ADV to PCC440 programming.

Description

Keywords: DRC, design, rules, check, Map, PowerPC, PPC, 440, 400, MHz

When I create a PowerPC 440 design through Base System builder, I receive the following DRC errors:

ERROR:PhysDesignRules:1690 - Incomplete PLL_ADV to PCC440 programming. The signal clk_400_0000MHzPLL0 for the CPMC440CLK
pin of PPC440 comp ppc440_0/ppc440_0/PPC440_i is driven by PLL_ADV comp
clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst CLKOUT5 pin but the
corresponding CLKOUT4_DESKEW_ADJUST attribute is not set NONE.
ERROR:Pack:1642 - Errors in physical DRC.

Solution

The DRC errors are invalid. You can work around the problem by swapping the "problem" CLKOUT pin on the clock generator core with CLKOUT0. For example, the DRC error is complaining about the 400 MHz clock. Here is a portion of the clock generator instance from the MHS file:

BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT0_FREQ = 100000000
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = PLL0_ADJUST
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_CLKOUT1_FREQ = 125000000
:
:
PORT CLKIN = dcm_clk_s
PORT CLKOUT0 = clk_100_0000MHzPLL0_ADJUST
PORT CLKOUT1 = clk_125_0000MHz
PORT CLKOUT2 = clk_133_3333MHzPLL0_ADJUST
PORT CLKOUT3 = clk_200_0000MHz90PLL0_ADJUST
PORT CLKOUT4 = clk_200_0000MHzPLL0
PORT CLKOUT5 = clk_200_0000MHzPLL0_ADJUST
PORT CLKOUT6 = clk_400_0000MHzPLL0
PORT RST = net_gnd
PORT LOCKED = Dcm_all_locked
END

Change the clock generator instance in the MHS to:

BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT6_FREQ = 100000000
PARAMETER C_CLKOUT6_PHASE = 0
PARAMETER C_CLKOUT6_GROUP = PLL0_ADJUST
PARAMETER C_CLKOUT6_BUF = TRUE
PARAMETER C_CLKOUT1_FREQ = 125000000
:
:
PARAMETER C_CLKOUT5_BUF = TRUE
PARAMETER C_CLKOUT0_FREQ = 400000000
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = PLL0
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER HW_VER = 3.01.a
PORT CLKIN = dcm_clk_s
PORT CLKOUT6 = clk_100_0000MHzPLL0_ADJUST
PORT CLKOUT1 = clk_125_0000MHz
PORT CLKOUT2 = clk_133_3333MHzPLL0_ADJUST
PORT CLKOUT3 = clk_200_0000MHz90PLL0_ADJUST
PORT CLKOUT4 = clk_200_0000MHzPLL0
PORT CLKOUT5 = clk_200_0000MHzPLL0_ADJUST
PORT CLKOUT0 = clk_400_0000MHzPLL0
PORT RST = net_gnd
PORT LOCKED = Dcm_all_locked
END


This problem is scheduled to be fixed in 12.1.
AR# 33223
Date Created 07/30/2009
Last Updated 07/30/2009
Status Active
Type General Article