AR# 33224: Virtex-6 FPGA FIFO - First read after reset is incorrect
Virtex-6 FPGA FIFO - First read after reset is incorrect
When reading from a FIFO in a Virtex-6 FPGA design which is properly constrained and passes timing analysis, the first word read after reset is sometimes incorrect.
The workaround is to modify the design using the following guidelines:
1. Whenever reset is asserted, ensure that both RDEN and WREN have been deasserted for at least four WRCLK and RDCLK cycles. *
2. Always ensure that RST is synchronous to RDCLK. **
*This information has been added to v1.3 of the Virtex-6 FPGA Memory Resources User Guide. It applies to all Virtex-6 Production and Engineering Sample devices. ** This guideline only applies to devices which have Errata documents referencing this Answer Record specifically, and does not apply to Production devices. Please see the errata for your device to determine if this guideline must be followed. The Virtex-6 FPGA Errata can be found here: http://www.xilinx.com/support/documentation/virtex-6.htm