This Answer Record contains the Release Notes and Known Issues for System Generator for DSP 11.3.
For System Generator for DSP Release Notes from other versions, see (Xilinx Answer 29595)
This README Answer Record contains installation instructions and a list of the issues fixed in the System Generator for DSP 11.3 Update.
A successful installation of ISE Design Suite 11.3 changes your design tools version number to 11.3. (Verify by running xlVersion at the MATLAB prompt.)
1) Download "Xilinx_11.3_ISE_DS_<platform>.tar" from:
2) Untar the archive. For more information about tar files, see (Xilinx Answer 32818).
3) Open the untarred archive and run "xsetup(.exe)".
4) Select the root location of ISE Design Suite as your destination directory (that is, C:\Xilinx\11.1 or /opt/Xilinx/11.1).
Note: XilinxUpdate which is run from ISE Design Suite can also be used to download and install updates. Please see the Help System for more information on running XilinxUpdate.
For more information on what other products are included in this update, see (Xilinx Answer 33216).
Release Notes and Known Issues in System Generator for DSP 11.3
Please read the documentation, because it answers questions you might have about changes to the functionality or the appearance from previous versions of System Generator for DSP.
The System Generator User Guide is accessible in PDF format at:
11.3 System Generator Enhancements
To see a list and description of the new features in 11.3, see the System Generator User Guide:
Product Change Notice
Starting with the 11.2 release, further development of the AccelDSP synthesis tool has been discontinued.
You can continue to use this version of the tool with ISE Design Suite 11. The tool will not be included in ISE Design Suite 12.
|(Xilinx Answer 23614)||Why does the design fail to generate when using an IP core? Why do I receive "Error 0001: caught standard exception" during generation?|
Installation and setup
|(Xilinx Answer 17966)||What software is required to install System Generator for DSP?|
|(Xilinx Answer 32257)||How can I tell if the DSP Tools are installed and configured for use in MATLAB?|
|(Xilinx Answer 24842)||How can I switch between multiple versions of System Generator for one MATLAB installation?|
|(Xilinx Answer 32258)||How can I install just the DSP Tools without reinstalling all of the ISE Design Tools?|
|(Xilinx Answer 25306)||Which version of System Generator supports the latest version of MATLAB?|
|(Xilinx Answer 33788)||How does System Generator license checkout work?|
MATLAB and Simulink interaction
|(Xilinx Answer 31933)||Why do I receive an error message stating "continuous sample times are not allowed" when driving a Simulink Spectrum Scope with Xilinx System Generator blocks?|
|(Xilinx Answer 30131)||Why is the sample rate passed to Simulink blocks from my gateway out different than the sample rate passed to my System Generator blocks?|
|(Xilinx Answer 21750)||Why do I receive a "xlSimulationRequired" or "Reference to a cleared variable sysgen_return_status" error when I try to generate the design?|
|(Xilinx Answer 23000)||An indeterminate input data (also known as a NAN) error occurs when design is simulated.|
|(Xilinx Answer 24616)||Why am I unable to access the quantization parameters in the FDATool in System Generator?|
|(Xilinx Answer 25255)||Why do I receive a Simulink message stating, "Use of this data type requires a fixed-point license, but license checkout failed"?|
|(Xilinx Answer 23328)||What is the recommended Simulink simulation solver? Why do I see incorrect behavior when a fixed-step solver is used?|
|(Xilinx Answer 32810)||Why does my data not appear downsampled when I use "first value of frame" with a latency of 0 with the downsample block?|
|(Xilinx Answer 32856)||Why do I receive an internal error or see MATLAB crash if I use the Simulink Simulation option "Accelerator"?|
Third-Party Synthesis Tools
|(Xilinx Answer 24273)||I cannot generate an NGC, Bitstream, Timing Analysis, or Hardware in the Loop target when using Synplify as my synthesis tool. Why?|
|(Xilinx Answer 29170)||Why are there simulation mismatches at the beginning of the HDL simulation generated from System Generator for DSP when Synplify is used for synthesis?|
|(Xilinx Answer 24257)||Why do I see an instantiated register called "xlpersistentdff" in a System Generator for DSP design?|
|(Xilinx Answer 19599)||JTAG Hardware Co-Simulation with non-Xilinx parts in the chain causes error.|
|(Xilinx Answer 29430)||Why do I receive a standard exception error message when I generate my model?|
|(Xilinx Answer 33462)||Why is the list of MATLAB versions blank when I launch the Configuration Manager (MATLAB Chooser) for System Generator?|
|(Xilinx Answer 31934)||When running a MATLAB Student Edition, why do I receive the error message "Error evaluating 'OpenFcn' callback of Xilinx Gateway In Block block (mask)"?|
|(Xilinx Answer 32172)||Why am I unable to search the System Generator documentation and copy text from it when using MATLAB R2008a?|
|(Xilinx Answer 33122)||Why does the Multiplier block use fabric when I specified "use embedded multipliers"?|
|(Xilinx Answer 33125)||Why do I receive NGDBuild errors regarding illegal buffers when I generate my EDK Processor design to a Hardware co-simulation target?|
|(Xilinx Answer 33361)||Why do I receive a standard exception error message when I try to generate my FSL PCORE?|
|(Xilinx Answer 33482)||Why do I receive a standard exception error when generating my design using shared memory blocks?|
|(Xilinx Answer 33466)||Why do I receive a hardware timeout when I use the Interleaver/De-Interleaver 5.0?|
|(Xilinx Answer 33909)||Why do I sometimes see cycle mismatches between my Simulink and HDL simulations when I use a really small sample period?|
|(Xilinx Answer 32173)||Why is the System Generator blockset empty when I attempt to open it in Simulink when running on Linux?|
|(Xilinx Answer 33059)||Why do I receive an error message that an Unsupported version of ISE is found even though I have ISE 11 installed?|