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AR# 33247

11.2 Constraints System - Constraints derived from Virtex-5 PLL incorrect for Virtex-6 MMCM


When converting a design from Virtex-5 to Virtex-6 FPGA, the period constraints applied to the PLL are incorrect derived on the output side of the Virtex-6 FPGA MMCM.

Is this a known issue?


This issue has been fixed with the 12.1 release of ISE Design Suite.
AR# 33247
Date 05/23/2014
Status Archive
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
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