This answer record contains the Release Notes and Known Issues list for the CORE Generator software and LogiCORE IP Video On Screen Display Core.
The following information is listed for each version of the core:
LogiCORE IP Video On Screen Display:
General LogiCORE IP Video On Screen Display Issues
| (Xilinx Answer 45913) | Does the OSD support different input frame sizes and rates? |
| (Xilinx Answer 34828) | How do I simulate my Video IP pcore in EDK? |
| (Xilinx Answer 50420) | Why are operations limited to even pixel boundaries when using the OSD in 2 channel mode? |
| (Xilinx Answer 53619) | Why does the background change to another color, when a GPU layer is enabled? |
| (Xilinx Answer 54250) | Why does the Windows 32-bit C-Model crash when running the Example 3? |
| (Xilinx Answer 51231) | Why can I not target the 7 series Lower Power Devices? | |
| (Xilinx Answer 51247) | Why did the software driver stop working with my Video On Screen Display (OSD) core after updating to the latest version of the ISE Design Suite? |
| (Xilinx Answer 51231) | Why can I not target the 7 series Lower Power Devices? | |
| (Xilinx Answer 50909) | 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? | |
| (Xilinx Answer 51247) | Why did the software driver stop working with my Video On Screen Display (OSD) core after updating to the latest version of the ISE Design Suite? |
| (Xilinx Answer 57278) | What is the valid range for the Global Alpha Value for each layer? |
| (Xilinx Answer 64661) | Why does the AXI Stream reset ARESETn seems to hold all control registers in reset? |
| (Xilinx Answer 57278) | What is the valid range for the Global Alpha Value for each layer? |
| (Xilinx Answer 64661) | Why does the AXI Stream reset ARESETn seems to hold all control registers in reset? |
LogiCORE IP Video On Screen Display v5.00.a
Supported Devices (ISE)
Supported Devices (Vivado)
New Features
Bug Fixes
Known Issues (ISE)
| (Xilinx Answer 51231) | Why can I not target the 7 series Lower Power Devices? |
| (Xilinx Answer 51247) | Why did the software driver stop working with my Video On Screen Display (OSD) core after updating to the latest version of the ISE Design Suite? |
| (Xilinx Answer 57278) | What is the valid range for the Global Alpha Value for each layer? |
Known Issues (Vivado)
| (Xilinx Answer 51231) | Why can I not target the 7 series Lower Power Devices? |
| (Xilinx Answer 50909) | 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? |
| (Xilinx Answer 51247) | Why did the software driver stop working with my Video On Screen Display (OSD) core after updating to the latest version of the ISE Design Suite? |
| (Xilinx Answer 57278) | What is the valid range for the Global Alpha Value for each layer? |
LogiCORE IP Video On Screen Display v4.00.a
Supported Devices (ISE)
Supported Devices (Vivado)
New Features
Bug Fixes
Known Issues
| (Xilinx Answer 51247) | Why did the software driver stop working with my Video On Screen Display (OSD) core after updating to the latest version of the ISE Design Suite? |
LogiCORE IP Video On Screen Display v3.0
Supported Devices
New Features
Bug Fixes
Known Issues
| (Xilinx Answer 47063) | Why does the OSD fail to generate if the Bits Per Pixel Color Depth is set to 2? |
| (Xilinx Answer 47897) | How do I write my Font Table into using the GPP Interface? |
| (Xilinx Answer 51247) | Why did the software driver stop working with my Video On Screen Display (OSD) core after updating to the latest version of the ISE Design Suite? |
LogiCORE IP Video On Screen Display v2.0
| (Xilinx Answer 33412) | Why does the text zoomed to 2x, 4x, or 8x display incorrectly? |
| (Xilinx Answer 33398) | Why do I receive a warning about a missing top level when generating the EDK Pcore interface? |
| (Xilinx Answer 33582) | Why do the function arguments of XOSD_SetBlankPolarity function say priority instead of polarity? |
| (Xilinx Answer 33907) | Why does the GUI allow a height and width range of 8 to 16 for the FONT RAM size? |
| (Xilinx Answer 34356) | Why is the vfbc_wd_clk output always low? |
| (Xilinx Answer 34380) | What is the clk_core port? |
| (Xilinx Answer 38505) | Why do I receive an "XST failed" error when I set Text Options, Number of Strings or String Length to zero? |
| (Xilinx Answer 36177) | Why does the OSD fail to generate when targeting large instruction sizes, string lengths or number of strings, when targeting Spartan-6 or Virtex-6 devices? |
| (Xilinx Answer 35635) | Why is the layer control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6 FPGA? |
| (Xilinx Answer 38497) | Why do I see artifacts around my Text and Boxes, when using the OSD graphics controller in 3 Channel Mode? |
| (Xilinx Answer 38728) | Why is the Video On Screen Display (OSD) so large when I use the pcore interface after applying the v1.0 Rev3 patch in 12.x? |
| (Xilinx Answer 43645) | Why do some of my VFBC layers fail to appear on the XSVI output interface? |
| (Xilinx Answer 51247) | Why did the software driver stop working with my Video On Screen Display (OSD) core after updating to the latest version of the ISE Design Suite? |
LogiCORE IP Video On Screen Display v1.0
There is a v1.0 rev5patch available in (Xilinx Answer 35635). This patch is intended to fix issues listed below as (Xilinx Answer 33412), (Xilinx Answer 38495), (Xilinx Answer 36177), (Xilinx Answer 38497), (Xilinx Answer 38498), and (Xilinx Answer 38728).
| (Xilinx Answer 33412) | Why does the text zoomed to 2x, 4x, or 8x display incorrectly? |
| (Xilinx Answer 33398) | Why do I receive a warning about a missing top level when generating the EDK Pcore interface? |
| (Xilinx Answer 33582) | Why do the function arguments of XOSD_SetBlankPolarity function say priority instead of polarity? |
| (Xilinx Answer 33907) | Why does the GUI allow a height and width range of 8 to 16 for the FONT RAM size? |
| (Xilinx Answer 34356) | Why is the vfbc_wd_clk output always low? |
| (Xilinx Answer 34380) | What is the clk_core port? |
| (Xilinx Answer 38505) | Why do I get an XST failed error when I set Text Options, Number of Strings or String Length to zero? |
| (Xilinx Answer 36177) | Why does the OSD fail to generate when targeting large instruction sizes, string lengths or number of strings, when targeting Spartan-6 or Virtex-6? |
| (Xilinx Answer 35635) | Why is the layer control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6 FPGA? |
| (Xilinx Answer 38497) | Why do I see artifacts around my Text and Boxes, when using the OSD graphics controller in 3 Channel Mode? |
| (Xilinx Answer 38728) | Why is the Video On Screen Display (OSD) so large when I use the pcore interface after applying the v1.0 Rev3 patch in 12.x? |
| AR# 33257 | |
|---|---|
| Date | 06/10/2015 |
| Status | Archive |
| Type | Release Notes |
| IP | |