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AR# 33258

LogiCORE IP DisplayPort - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues list for the CORE Generator tool and LogiCORE IP Display Port Core.

The following information is listed for each version of the core:

  • New Features
  • Bug Fixes
  • Known Issues

LogiCORE IP DisplayPort Lounge:

http://www.xilinx.com/products/ipcenter/EF-DI-DISPLAYPORT.htm

Solution

General LogiCORE IP DisplayPort Issues


(Xilinx Answer 42953) Design Advisory Master Answer Record for LogiCORE IP DisplayPort
(Xilinx Answer 34210) How do I connect the Display Port Core to my DisplayPort connector?
(Xilinx Answer 44843) Does the DisplayPort I2C over AUX support clock stretching for slower I2C slave?
(Xilinx Answer 46820) Does the Xilinx DisplayPort IP support eDP and features like Panel Self Refresh?
(Xilinx Answer 57950) Support has been removed from ISE in 14.7


LogiCORE IP DisplayPort v3.2


There is a v3.2 rev8 patch available; see (Xilinx Answer 53422).
This patch is intended to fix issues listed below in (Xilinx Answer 53538), (Xilinx Answer 53539), (Xilinx Answer 55359), (Xilinx Answer 56683), and (Xilinx Answer 57399).


  • Initial release in ISE 14.2 and Vivado 2012.2 tools

Supported Devices (ISE)


  • Virtex-7
  • Kintex-7
  • Artix-7
  • Virtex-6 XC LXT/SXT/HXT
  • Spartan-6 XC LXT
  • Spartan-6 XA LXT

Supported Devices (Vivado)


  • Virtex-7
  • Kintex-7

New Features


  • ISE Design Suite 14.2 design tools support
  • Secondary Channel Audio support
  • DisplayPort v1.2 5.4 Gb/s
  • Added support for IIC interfaces faster than 100kb/s

Resolved Issues

CR 658659Fix for logical error in edid_iic.v example design
CR 659178Fix for Event Status register appearing at 0x20 instead of 0x02
CR 665316Fix for reply count register (0x13C) not correctly updating with the number of reply transactions received
CR 665979Fix for SCL 50% duty cycle not being maintained when the clock speed is set to 1kbps
CR 666220Fix for master clock selection logic when I2C speed control register is configured as 0xFF
(Xilinx Answer 47818)Why does the AUX REPLY_STATUS register remain as REPLY_IN_PROGRESS even when an HDP even has occurred?
(Xilinx Answer 50125)Why does the DisplayPort core Hardware validation list the DNMEG_V5_T_PCIE board, when Virtex-5 FPGA is not supported?

Known Issues (ISE)

(Xilinx Answer 42952) Virtex-5 device support has been removed
(Xilinx Answer 42810) Why does the reference design have timing violations?
(Xilinx Answer 52296) Is a DCM or PLL required to generate the RXUSRCLK2 for the Spartan-6 GTP?
(Xilinx Answer 52299) Why is a -2 or -3 part required to support 5.4 Gb/s in 7-Series FPGAs?
(Xilinx Answer 53538) Why does the DisplayPort Sink IIC Controller hold the SCL line in some cases when large amounts of noise are introduced into it via the AUX channel input?
(Xilinx Answer 53539) Why does the DisplayPort Source Stop sending audio after a reset?
(Xilinx Answer 51964) Clocking Structure for GTP 2-Byte Mode Interface
(Xilinx Answer 54867) Missing FORCE_DUAL_PIXEL parameter
(Xilinx Answer 56168) Error in Simulation - Test Failed when targeting Artix-7
(Xilinx Answer 56138) Why do I not get any output when using the BUFIO2 with a DIVIDE = 2?
(Xilinx Answer 55359) Noise on the AUX Channel causes the Core AUX State Machine to Hang
(Xilinx Answer 56683) Sink Core Hangs During Write/Read
(Xilinx Answer 57399) VESA Spec Termination Scheme Causes Corruption on the AUX State Machine
(Xilinx Answer 57950) Support has been removed from ISE in 14.7

Known Issues (Vivado)

(Xilinx Answer 52296) Is a DCM or PLL required to generate the RXUSRCLK2 for the Spartan-6 GTP?
(Xilinx Answer 52299) Why is a -2 or -3 part required to support 5.4 Gb/s in 7 Series FPGAs?
(Xilinx Answer 53538) Why does the DisplayPort Sink IIC Controller hold the SCL line in some cases when large amounts of noise are introduced into it via the AUX channel input?
(Xilinx Answer 53539) Why does the DisplayPort Source Stop sending audio after a reset?
(Xilinx Answer 51964) Clocking Structure for GTP 2-Byte Mode Interface
(Xilinx Answer 54867) Missing FORCE_DUAL_PIXEL parameter
(Xilinx Answer 56168) Error in Simulation - Test Failed when targeting Artix-7
(Xilinx Answer 56138) Why do I not get any output when using the BUFIO2 with a DIVIDE = 2?
(Xilinx Answer 55359) Noise on the AUX Channel causes the Core AUX State Machine to Hang
(Xilinx Answer 56683) Sink Core Hangs During Write/Read
(Xilinx Answer 57399) VESA Spec Termination Scheme Causes Corruption on the AUX State Machine

LogiCORE IP DisplayPort v3.1


  • Initial release in ISE 14.1 and Vivado 2012.1 tools

Supported Devices (ISE)

  • Virtex-7
  • Kintex-7
  • Virtex-6 XC LXT/SXT/HXT
  • Spartan-6 XC LXT
  • Spartan-6 XA LXT

Supported Devices (Vivado)

  • Virtex-7
  • Kintex-7

New Features

  • ISE Design Suite 14.1 design tools support
  • Secondary Channel Audio support
  • DisplayPort v1.2, 5.4 Gb/s

Resolved Issues

(Xilinx Answer 43176) Why is the CORE_ID register different for the Source and Sink cores?
(Xilinx Answer 47096) Why does the DisplayPort sink fail to complete an AUX to IIC (I2C) write that is greater than 6 bytes?
(Xilinx Answer 45278) Why do I receive an error in MAP for the Hot Plug Detect (HPD) pin, when trying to target Kintex-7?

Known Issues (ISE)

(Xilinx Answer 42952) Virtex-5 device support has been removed
(Xilinx Answer 42810) Why does the reference design have timing violations?
(Xilinx Answer 47818) Why does the AUX REPLY_STATUS register remain as REPLY_IN_PROGRESS even when an HDP even has occurred?
(Xilinx Answer 50125) Why does the DisplayPort core Hardware validation list the DNMEG_V5_T_PCIE board, when Virtex-5 FPGA is not supported?
(Xilinx Answer 52299) Why is a -2 or -3 part required to support 5.4 Gb/s in 7 Series FPGAs?
(Xilinx Answer 53538) Why does the DisplayPort Sink IIC Controller hold the SCL line in some cases when large amounts of noise are introduced into it via the AUX channel input?
(Xilinx Answer 53539) Why does the DisplayPort Source Stop sending audio after a reset?
(Xilinx Answer 54867) Missing FORCE_DUAL_PIXEL parameter

Known Issues (Vivado)

(Xilinx Answer 47265) Why does Synthesis fail when the target language is set to VHDL?
(Xilinx Answer 47818) Why does the AUX REPLY_STATUS register remain as REPLY_IN_PROGRESS even when an HDP even has occurred?
(Xilinx Answer 50125) Why does the DisplayPort core Hardware validation list the DNMEG_V5_T_PCIE board, when Virtex-5 FPGA is not supported?
(Xilinx Answer 52299) Why is a -2 or -3 part required to support 5.4 Gb/s in 7-Series FPGAs?
(Xilinx Answer 53538) Why does the DisplayPort Sink IIC Controller hold the SCL line in some cases when large amounts of noise are introduced into it via the AUX channel input?
(Xilinx Answer 53539) Why does the DisplayPort Source Stop sending audio after a reset?
(Xilinx Answer 54867) Missing FORCE_DUAL_PIXEL parameter

LogiCORE IP DisplayPort v2.3


  • Initial release in ISE Design Suite 13.2

Supported Devices
  • Virtex-7
  • Kintex-7
  • Virtex-6 XC LXT/SXT/HXT
  • Spartan-6 XC LXT
  • Spartan-6 XA LXT

New Features
  • ISE Design Suite 13.2 support

Resolved Issues

CR 610594Tx framing logic does not send last byte of line data on to main link.
CR 608226i_last_pixel , i_line_doneandi_sterring_count registers have CDC issue.
CR 605875Issue in I2C Write burst to additional I2C slave.
CR 593604Fully packed TU logic fixed.
CR 593470Sink response with valid data for address only write command with MOT set to '1'
CR 592998Interrupt clear on read to interrupt status register logic fixed.
CR 591942no-video assertion looks at wrong bit selection of vbid.
CR 587716Sink core:AUX Write Status_Request transaction needs to be handled.
CR 587715Sink core: SYMBOL_ERROR_COUNT register implementation is incorrect.
CR 582256Source: User/framing logic misbehaves with 1680 pixel frame @ 10bpc, 4 lanes @ 2.7G.
CR 573034Sink core: DPCD structure made accessible from APB/AXI for advanced users.

Known Issues

(Xilinx Answer 42952) Virtex-5 device support has been removed
(Xilinx Answer 42810) Why does the reference design have timing violations?
(Xilinx Answer 43176) Why is the CORE_ID register different for the Source and Sink cores?
(Xilinx Answer 45278) Why do I get an error in MAP for the Hot Plug Detect (HPD) pin, when trying to target Kintex-7?
(Xilinx Answer 47096) Why does the DisplayPort sink fail to complete an AUX to IIC (I2C) write that is greater than 6 bytes?
(Xilinx Answer 47818) Why does the AUX REPLY_STATUS register remain as REPLY_IN_PROGRESS even when an HDP even has occurred?
(Xilinx Answer 50125) Why does the DisplayPort core Hardware validation list the DNMEG_V5_T_PCIE board, when Virtex-5 FPGA is not supported?

LogiCORE IP DisplayPort v2.2


  • Initial release in ISE Design Suite 13.1

Supported Devices

  • Virtex-6 XC LXT/SXT/HXT
  • Spartan-6 XC LXT
  • Spartan-6 XA LXT
  • Virtex-5 XC LXT/SXT/TXT/FXT

New Features

  • ISE Design Suite 13.1 support

Resolved Issues

CR 561918Spartan-6 and Virtex-6 FPGA unified wrapper files are needed.
CR 580813Response with min number of sync pulses is ignored by source.
CR 581723With some configurations source transmits zero length TUs that affects display.
CR 582925Virtex-5 FPGA with legacy interface (APB) is needed.
CR 587682Handshake mismatching between I2C sink and AUX response causes continuous I2C defers.
CR 587685The M value generated in dual-pixel mode is 1/2 the expected value.
CR 587714Video interrupt is generated immediately after no-video. Delayed the assertion for proper MSA availability.
CR 587715Symbol error counter for lane 2 and lane 3 has initialization issue.
CR 587722PRBS7 connectivity is not proper in Virtex-6 PHY.

Known Issues

(Xilinx Answer 35037) How do I use the two vid_enable output pins on the Display Port Sink core?
(Xilinx Answer 35075) What are the MAX_LINK_RATE, MAX_LANE_COUNT and other values defined by the VESA Display Port v1.1a specification?
(Xilinx Answer 44843) Does the DisplayPort I2C over AUX support clock stretching for slower I2C slave?
(Xilinx Answer 47096) Why does the DisplayPort sink fail to complete an AUX to IIC (I2C) write that is greater than 6 bytes?
(Xilinx Answer 50125) Why does the DisplayPort core Hardware validation list the DNMEG_V5_T_PCIE board, when Virtex-5 FPGA is not supported?

LogiCORE IP DisplayPort v2.1


  • Initial release in ISE Design Suite 12.3

Supported Devices

  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5 FXT
  • Spartan-6 LXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6 HXT

New Features
  • ISE Design Suite 12.3 support

Resolved Issues

CR 570896GTP_DUAL_X0Y0 needs GTP_DUAL_X0Y1 instantiated. As per recommendation constraints are updated.
CR 568660Writes to DPCD address 0x0600 return NACK.
CR 565479Pixel loss is seen when using 10/8 BPC in YCbCr422 format.
CR 559333A rare case occurring where data is getting unaligned after training is done.

Known Issues

(Xilinx Answer 35037) How do I use the two vid_enable output pins on the Display Port Sink core?
(Xilinx Answer 35075) What are the MAX_LINK_RATE, MAX_LANE_COUNT and other values defined by the VESA DisplayPort v1.1a specification?
(Xilinx Answer 44843) Does the DisplayPort I2C over AUX support clock stretching for slower I2C slave?
(Xilinx Answer 47096) Why does the DisplayPort sink fail to complete an AUX to IIC (I2C) write that is greater than 6 bytes?
(Xilinx Answer 50125) Why does the DisplayPort core Hardware validation list the DNMEG_V5_T_PCIE board, when Virtex-5 FPGA is not supported?

LogiCORE IP DisplayPort v1.3


  • Initial release in ISE Design Suite 12.2

New Features
  • ISE 12.2 design tools support
  • Virtex-6 FPGA support

Resolved Issues

CR # 557442When connecting the Rx and Tx example designs together, contention occurs on the AUX bus. This has been resolved in 12.2.
CR # 557203The top-level file contains the ports for both Tx and Rx links, resulting in port mismatch errors when Tx or Rx core is generated. This has been resolved in 12.2.
CR #: 557137The lane count in defines.v file is hard-coded to a value of 4. This has been changed to take the value configured during core generation.
CR #: 557134Different file names have been created for Tx and Rx example designs in 12.2.
(Xilinx Answer 34829) Why do I receive an error about the GTP_DUAL, when I target a Virtex-5 TXT device?
CR #: 554267The ejava files for the TX, RX and TX RX have been updated to use a GTX wrapper when the selected device is Virtex-5 FXT or Virtex-5 TXT.
CR #: 559502The device name in the xst_scr.ejava file is hard-coded to a specific value. This has been updated to match the device. selected by the user during core generation.
CR #: 538464The .vho file for the source core was not formatted correctly, resulting in a syntax error during synthesis.
(Xilinx Answer 33888)LogiCORE IP Display Port v1.1 Why does the example design not meet timing when I target a Spartan-6 device?
(Xilinx Answer 35403)Why does the core fail to train when the MIN_PRE_EMPHASIS register is set to any value other than zero.

Known Issues

(Xilinx Answer 35037) How do I use the two vid_enable output pins on the Display Port Sink core?
(Xilinx Answer 35075) What are the MAX_LINK_RATE, MAX_LANE_COUNT and other values defined by the VESA Display Port v1.1a specification?
(Xilinx Answer 44843) Does the DisplayPort I2C over AUX support clock stretching for slower I2C slave?

LogiCORE IP DisplayPort v1.2


  • Initial release in ISE Design Suite 12.1

New Features
  • ISE 12.1 design tools support
  • Addition of Secondary Channel Audio support
  • Virtex-6 FPGA support

Resolved Issues

(Xilinx Answer 33890) LogiCORE IP Display Port v1.1 - Why does my Display Port Receiver Sink core not work correctly when I have a single active lane and the user interface is forced to 2 bits wide?
CR #: 539132For the Sink core, when the user would set the user pixel width to 2 (0x010) and force the user pixel width to 2 (0x008) when the number of active lanes is only 1, the data would arrive to the user incorrectly.
(Xilinx Answer 33885)LogiCORE IP Display Port v1.1 - Why does my VHDL Instantiation template fail when I attempt to simulate or synthesize the transmitter source design?
(Xilinx Answer 33886)LogiCORE IP Display Port v1.1 - DCM Wrapper needs to be changed to use high-frequency mode for the Display Port Receiver Sink Example design to work properly under all circumstances.
(Xilinx Answer 33887)LogiCORE IP Display Port v1.1 - Why is my HSYNC timing incorrect when using the dual pixel mode for some frequencies?
(Xilinx Answer 34671)Why do I see a simulation error with the Display port example design 11.5?

Known Issues

(Xilinx Answer 33889) Where can I find the Getting Started Guide for the Display Port Core?
(Xilinx Answer 33888) LogiCORE IP Display Port v1.1 - Why does the example design not meet timing when I target a Spartan-6 device?
(Xilinx Answer 34829) Why do I receive an error about the GTP_DUAL, when I target a Virtex-5 TXT device?
(Xilinx Answer 35037) How do I use the two vid_enable output pins on the Display Port Sink core?
(Xilinx Answer 35075) What are the MAX_LINK_RATE, MAX_LANE_COUNT and other values defined by the VESA Display Port v1.1a specification?
(Xilinx Answer 35403) Why does the core fail to train when the MIN_PRE_EMPHASIS register is set to any value other than zero?
(Xilinx Answer 44843) Does the DisplayPort I2C over AUX support clock stretching for slower I2C slave?

LogiCORE IP DisplayPort v1.1


  • Initial release in ISE Design Suite 11.4

New Features
  • ISE Design Suite 11.4 support
  • Initial release

Resolved Issues
  • N/A

Known Issues

(Xilinx Answer 33885) Why does my VHDL Instantiation template fail when I try to simulate or synthesize my transmitter source design?
(Xilinx Answer 33886) Wrapper needs to be changed to use high-frequency mode for the Display Port Receiver Sink Example design to work properly under all circumstances.
(Xilinx Answer 33887) Why is my HSYNC timing incorrect when using the dual pixel mode for some frequencies?
(Xilinx Answer 33888) Why does the example design not meet timing when targeting a Spartan-6 device?
(Xilinx Answer 33889) Where can I find the Getting Started Guide for the Display Port core?
(Xilinx Answer 33890) Why does my Display Port Receiver Sink core not work correctly when I have a single active lane and the user interface is forced to 2-bits wide?
(Xilinx Answer 34671) Why do I see a simulation with the Display port example design 11.5?
(Xilinx Answer 34829) Why do I receive an error about the GTP_DUAL, when I target a Virtex-5 TXT device?
(Xilinx Answer 35037) How do I use the two vid_enable output pins on the Display Port Sink core?
(Xilinx Answer 35075) What are the MAX_LINK_RATE, MAX_LANE_COUNT and other values defined by the VESA Display Port v1.1a specification?
(Xilinx Answer 44843) Does the DisplayPort I2C over AUX support clock stretching for slower I2C slave?

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
47265 LogiCORE IP DisplayPort v3.1 (Vivado 2012.1) - Why does Synthesis fail when the target language is set to VHDL? N/A N/A
47096 LogiCORE IP DisplayPort v2.3 - Why does the DisplayPort sink fail to complete an AUX to IIC (I2C) write that is greater than six bytes? N/A N/A
46820 LogiCORE IP DisplayPort - Does the Xilinx DisplayPort IP support eDP and features like Panel Self Refresh? N/A N/A
45278 LogiCORE IP DisplayPort v2.3 - Why do I get an error in MAP for the Hot Plug Detect (HPD) pin, when trying to target Kintex-7 FPGA? N/A N/A
44843 LogiCORE IP DisplayPort v2.3 - Does the DisplayPort I2C over AUX support clock stretching for slower I2C slaves? N/A N/A
42953 Design Advisory Master Answer Record for LogiCORE IP DisplayPort N/A N/A
42952 Design Advisory for LogiCORE IP DisplayPort - Virtex-5 device support has been removed N/A N/A
42810 LogiCORE IP DisplayPort v2.3 - Why does the reference design have timing violations? N/A N/A
35075 LogiCORE IP Display Port v1.1 - What are the MAX_LINK_RATE, MAX_LANE_COUNT and other values defined by the VESA Display Port v1.1a specification? N/A N/A
34671 LogiCORE IP Display Port v1.1 - Why do I see a simulation error with the Display port example design in 11.5? N/A N/A
34210 LogiCORE IP Display Port - How do I connect the Display Port Core to my Display Port connector? N/A N/A
33888 LogiCORE IP Display Port v1.2 - The example design does not meet timing when I target a Spartan-6 device. Why? N/A N/A
33886 LogiCORE IP Display Port v1.1 - DCM Wrapper needs to be changed to use high-frequency mode for the Display Port Receiver Sink Example design to work properly under all cirumstances N/A N/A
47818 LogiCORE DisplayPort v2.3 - Why does the AUX REPLY_STATUS register remain as REPLY_IN_PROGRESS even when an HDP has occurred? N/A N/A
37194 LogiCORE DisplayPort – Which version of Display port supports VESA DisplayPort v1.2 (5.4Gbps Gen2) Standard? N/A N/A
51560 LogiCORE DisplayPort - How do I select the proper USER_PIXEL_WIDTH for my resolution? N/A N/A
52299 LogiCORE IP DisplayPort v3.2 - Why is a -2 or -3 part required to support 5.4 Gb/s in 7 Series FPGAs? N/A N/A
53422 LogiCORE IP DisplayPort v3.2 - Patch Updates for the DisplayPort N/A N/A
53538 LogiCORE IP DisplayPort v3.2 - Why does the DisplayPort Sink IIC Controller hold the SCL line in some cases when large amounts of noise are introduced into it via the AUX channel input? N/A N/A
53539 LogiCORE IP DisplayPort v3.2 - Why does the DisplayPort Source core Stop sending audio after a reset? N/A N/A
51964 LogiCORE IP DisplayPort v3.2 - Clocking Structure for GTP 2-Byte Mode Interface N/A N/A
55359 LogiCORE DisplayPort v3.2 - Noise on the AUX Channel causes the Core AUX State Machine to Hang N/A N/A
56138 LogiCORE IP DisplayPort v3.2 - Why do I not get any output when using the BUFIO2 with a DIVIDE = 2? N/A N/A
56168 LogiCORE DisplayPort v3.2 - Error in Simulation - Test Failed when targeting Artix-7 N/A N/A
56683 LogiCORE IP DisplayPort v3.2 - Sink Core Hangs During Write/Read N/A N/A
57399 Spartan-6 - LogiCORE IP DisplayPort v3.2 - VESA Specification Termination Scheme Causes Corruption on the AUX State Machine N/A N/A
60227 LogiCORE IP DisplayPort - What is the polarity of the User Data Interface Pins for the DisplayPort Source core? N/A N/A
57950 LogiCORE IP DisplayPort v3.2 - Support has been removed from ISE in 14.7 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46820 LogiCORE IP DisplayPort - Does the Xilinx DisplayPort IP support eDP and features like Panel Self Refresh? N/A N/A
43176 LogiCORE IP DisplayPort v2.3 - Why is the CORE_ID register different for the Source and Sink cores? N/A N/A
42952 Design Advisory for LogiCORE IP DisplayPort - Virtex-5 device support has been removed N/A N/A
42810 LogiCORE IP DisplayPort v2.3 - Why does the reference design have timing violations? N/A N/A
35403 LogiCORE DisplayPort core v1.2 - Why does the core fail to train when the MIN_PRE_EMPHASIS register is set to any value other than zero? N/A N/A
35075 LogiCORE IP Display Port v1.1 - What are the MAX_LINK_RATE, MAX_LANE_COUNT and other values defined by the VESA Display Port v1.1a specification? N/A N/A
35037 LogiCORE IP Display Port v1.1 - How do I use the two vid_enable output pins on the Display Port Sink core? N/A N/A
34671 LogiCORE IP Display Port v1.1 - Why do I see a simulation error with the Display port example design in 11.5? N/A N/A
34210 LogiCORE IP Display Port - How do I connect the Display Port Core to my Display Port connector? N/A N/A
33890 LogiCORE IP Display Port v1.1 - Why does my Display Port Receiver Sink core not work correctly when I have a single active lane and the user interface is forced to 2 bits wide? N/A N/A
33889 LogiCORE IP Display Port v1.1 - Where can I find the Getting Started Guide for the Display Port Core? N/A N/A
33888 LogiCORE IP Display Port v1.2 - The example design does not meet timing when I target a Spartan-6 device. Why? N/A N/A
33887 LogiCORE IP Display Port v1.1 - Why is my HSYNC timing incorrect when using the dual pixel mode for some frequencies? N/A N/A
33886 LogiCORE IP Display Port v1.1 - DCM Wrapper needs to be changed to use high-frequency mode for the Display Port Receiver Sink Example design to work properly under all cirumstances N/A N/A
33885 LogiCORE IP Display Port v1.1 - Why does my VHDL Instantiation template fail when I attempt to simulate or synthesize the transmitter source design? N/A N/A
47265 LogiCORE IP DisplayPort v3.1 (Vivado 2012.1) - Why does Synthesis fail when the target language is set to VHDL? N/A N/A
33258 LogiCORE IP DisplayPort - Release Notes and Known Issues N/A N/A
AR# 33258
Date Created 08/10/2009
Last Updated 07/04/2016
Status Active
Type Release Notes
IP
  • DisplayPort