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AR# 33290: 11.2 EDK - "WARNING:Place:971 - A GCLK / GCLK clock component pair have been found that are not placed at an optimal GCLK / GCLK site pair..."
11.2 EDK - "WARNING:Place:971 - A GCLK / GCLK clock component pair have been found that are not placed at an optimal GCLK / GCLK site pair..."
The ML507 BSB design generates the following warnings when implemented with XPS_LL_TEMAC:
WARNING:Place:971 - A GCLK / GCLK clock component pair have been found
that are not placed at an optimal GCLK / GCLK site pair. The GCLK component
is placed at site .
The corresponding GCLK component is placed
at site . The GCLK site can use the fast path to the other
GCLK if both the GCLK components are placed in the same half of the device
(TOP or BOTTOM). You may want to analyze why this problem exists and
correct it. This is not an error so processing will continue.
WARNING:Route:466 - Unusually high hold time violation detected among 23 connections. The top 20 such instances are printed below. The router will continue and try to fix it
The pin for the MII TX clock is in the upper half of the chip and the system clocking is being placed in the lower half of the chip.
The BUFGMUX that combines the input from the pin and the clocking circuitry cannot be in the same half of the chip as the two signals that feed it.
As a result it is not easily possible to solve this problem for this board design.
This warning can be ignored only if the tools can resolve the timing and it successfully meets the timing constraints at the end of PAR.
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