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AR# 33302

LogiCORE IP XAUI v9.1 and v9.1 rev1 - Release Notes and Known Issues for ISE Design Suite 11.3 and 11.5

Description

This Answer Record contains the Release Notes for the LogiCORE IP XAUI v9.1 Core, which was released in the ISE Design Suite 11.3, and v9.1 rev1 Core, which was released in ISE Design Suite 11.5.This Answer Recordincludes the following:
  • New Features
  • Bug Fixes
  • Known Issues

For installation instructions, general CORE Generator interface known issues, and design tools requirements, see the IP Release Notes Guide: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

For LogiCORE XAUI Frequently Asked Questions (FAQ), see (Xilinx Answer 33596).

Solution

New Features in v9.1
  • 11.3 ISE Design Suite support
  • Virtex-6 Lower Power device support
  • Virtex-6 HXT device support
  • Spartan-6 LXT device support

Resolved Issues in v9.1
  • (Xilinx Answer 33135) LogiCORE IP XAUI v8.2 - Incorrect Virtex-6 FPGA GTX attribute when not using the IEEE state machines

Resolved Issues in v9.1 rev1
  • (Xilinx Answer 33649)LogiCORE XAUI v9.1 and RXAUI v1.1 - Virtex-6 FPGA GTX default setting for TXDIFFCTRL could result in electrical idle condition
  • (Xilinx Answer 34163) - LogiCORE IP XAUI v9.1 - The Spartan-6 FPGA Example Design does not implement the DCM_SP attribute setting for "CLK_FEEDBACK"
  • (Xilinx Answer 34159) - LogiCORE IP XAUI v9.1 - The Virtex-6 FPGA Example Design MMCMs can cause DRC errors
  • (Xilinx Answer 33504) - Spartan-6 FPGA GTP Transceiver: Channel Bonding signals fail timing

Known Issuesin v9.1 rev1
  • Virtex-6 and Spartan-6 device solutions are pending hardware validation.
  • The XAUI core v9.1rev1 was the last version totarget Virtex-6 GTX CES silicon. XAUI v9.2 and later versions of the core support production silicon with production GTX attributes.
  • (Xilinx Answer 24678) - Virtex-4 FPGA GT11 SmartModel Simulation - TX serial output skewed in SimPrims Timing simulation
  • (Xilinx Answer 33486) - LogiCORE IP XAUI v9.1 and RXAUI v1.1 - Update needed for reset logic in block level for Spartan-6 Device GTP and Virtex-6 Device GTX wrappers
  • (Xilinx Answer 33488) - LogiCORE IP XAUI v9.1 and RXAUI v1.1 - Virtex-6 FPGA GTX powerdown reset logic should be updated
  • (Xilinx Answer 33489) - LogiCORE IP XAUI v9.1 and RXAUI v1.1 - Timing Simulation Timeouts seen in Virtex-6 FPGA Example Design
  • (Xilinx Answer 33491) - LogiCORE IP XAUI v9.1 - Timeout seen in Spartan-6 FPGA Example Design Timing Simulation
  • (Xilinx Answer 33492) - LogiCORE IP XAUI v9.1 - Implementing Spartan-6 and Virtex-6 FPGA Examples Designs results in MAP errors for some device packages
  • (Xilinx Answer 33386) - 11.3 CORE Generator - Licenses for certain free cores are now included in the software install
  • (Xilinx Answer 36228) - LogiCORE IP XAUI v9.1 and v9.1 rev1 - Virtex-6 GTX_POWER_SAVE needs to be updated to target ISE 12.2

Linked Answer Records

Child Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43154 Spartan-6 FPGA GTP Transceiver - Reference clock phase noise mask N/A N/A
42807 Spartan-6 FPGA GTP Transceiver Wizard v1.10 - Release Notes and Known Issues for ISE 13.2 Software N/A N/A
41829 Spartan-6 FPGA GTP Transceiver Wizard v1.9 - Release Notes and Known Issues for ISE 13.1 software N/A N/A
41828 Spartan-6 FPGA GTP Transceiver Wizard v1.8 - Release Notes and Known Issues for ISE 12.4 software N/A N/A
41825 Spartan-6 FPGA GTP Transceiver Wizard v1.6 - Release Notes and Known Issues for ISE Software 12.2 N/A N/A
41824 Spartan-6 FPGA GTP Transceiver Wizard v1.5 - Release Notes and Known Issues for ISE Software 12.1 N/A N/A
34163 LogiCore IP XAUI v9.1 - The Spartan-6 FPGA Example Design does not implement the DCM_SP attribute setting for "CLK_FEEDBACK" N/A N/A
34159 LogiCORE IP XAUI v9.1 - The Virtex-6 FPGA Example Design MMCMs can cause DRC errors N/A N/A
33863 Spartan-6 FPGA GTP - PLL feedback divider settings in GTP N/A N/A
33649 LogiCORE XAUI v9.1 and RXAUI v1.1 - Virtex-6 FPGA GTX default setting for TXDIFFCTRL could result in electrical idle condition N/A N/A
33575 Spartan-6 FPGA - JTAG Configuration Setup For Designs Using GTPs N/A N/A
33572 Spartan-6 GTP Transceiver - GTPCLKOUT must be routed through a BUFIO N/A N/A
33504 Spartan-6 GTP Transceiver: Channel Bonding Signals Fail Timing N/A N/A
33492 LogiCORE XAUI v9.1 - Implementing Spartan-6 and Virtex-6 FPGA Examples Designs results in MAP errors for some device packages N/A N/A
33491 LogiCORE XAUI v9.1 - Timeout seen in Spartan-6 FPGA Example Design Timing Simulation N/A N/A
33489 LogiCORE XAUI v9.1 and RXAUI v1.1 - Timing Simulation Timeouts seen in Virtex-6 FPGA 64-bit Internal Interface Example Design N/A N/A
33488 LogiCORE XAUI v9.1 and RXAUI v1.1 - Virtex-6 FPGA GTX powerdown reset logic should be updated N/A N/A
33486 LogiCORE XAUI v9.1 and RXAUI v1.1 - Update needed for reset logic in block level for Spartan-6 Device GTP and Virtex-6 Device GTX wrappers N/A N/A
33386 11.3 CORE Generator - Licenses for certain free cores are now included in the software install N/A N/A
24678 Virtex-4 GT11 SmartModel Simulation - TX serial output skewed in SimPrims Timing simulation N/A N/A
AR# 33302
Date Created 09/10/2009
Last Updated 05/22/2012
Status Archive
Type Release Notes
Tools
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
IP
  • XAUI