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AR# 33353

Spartan-6 GTP Transceiver - Reference clock forwarding considerations and limitations

Description

This answer record discusses limitations on reference clock routing in the Spartan-6 FPGA GTP that need to be taken into consideration when routing a single reference clock from a dedicated IBUFDS_GTPA1 primitive to multiple GTP Transceivers.

Solution

In cases where both dedicated inputs are being used while both PLLs in the GTP_DUAL are being used, it is possible to drive each PLL from either reference clock. The only situation that this is not permitted is if CLK1 is being used to drive PLL0 and CLK0 is used to drive PLL1. This will result in neither PLL being able to achieve lock.

It is possible when routing from an IBUFDS associated with 1 GTP_DUAL and trying to route it to an adjacent GTP_DUAL, that the routing is not completed correctly by software. To work around this, it is recommended that users note which direction the clock will be routed and connect the reference clock to the associated port on the adjacent GTP_DUAL.

It is possible for the software to implement two east bound clock routes when only one exists in hardware. Customers need to note the source for their clocks and where they are intended to be routed before implementing. There is only a single path from a particular IBUFDS_GTPA1 to an adjacent GTP1CLKINEAST0/1.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33475 Virtex-6 FPGA GTX Transceiver - Known Issues and Answer Record List N/A N/A
AR# 33353
Date Created 04/14/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LXT