We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33367

11.3 PlanAhead - DRC is allowing signals connected to IBUFGDS to be placed at non-clock pins


Keywords:global, cc, gc, dcm

I have a design with differential clock inputs driving an IBUFGDS, which have unintentionally been placed at general I/O sites instead of clock pins. I ran DRC in PlanAhead, but received no errors. I do get errors in the implementation tools. Should not PlanAhead's DRCs catch this?


Yes, PlanAhead should catch this and will in a future version of the software. Currently, PlanAhead DRCs are not intended to be a sign-off tool, but are intended to catch as many violations as possible. Refer to (Xilinx Answer 32379).

AR# 33367
Date 09/01/2009
Status Active
Type General Article
Page Bookmarked