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MIG v3.2, Virtex-6 FPGA RLDRAMII - MAX tCK violations occur in simulation for -18 parts running at 370 MHz
When simulating the MIG v3.2 Virtex-6 FPGA RLDRAMII design for a -18 RLDRAMII device running at 370 MHz, MAX tCK violations occur in simulation.
For -18 parts running at 370 MHz, the maximum tCK is 2700 ps according to the Micron data sheet.
The MIG RLDRAMII design incorrectly sets tCK to 2702 due to a rounding error in the time period calculation.
This is only a rounding error and so the violation can be safely ignored.
This rounding error will be resolved in MIG v3.3 which will be available with IDS 11.4.
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