AR# 33377
|MIG v3.2, v3.3, Virtex-6 FPGA RLDRAMII - Design is unroutable when Debug Signals are turned on
Description
When I implement the MIG output for a Virtex-6 FPGA RLDRAMII design with Debug Signals enabled, errors similar to the following occur during PAR:
ERROR:Route:472 - This design is unroutable. To evaluate the problem please use fpga_editor.
Routing Conflict 1:
Net:u_rld_top/u_phy_top/u_phy_read_top/u_phy_read_stage1_cal/cq_num_load<3>
on pin DIADI8 on location RAMB18_X5Y104
Net:u_rld_top/u_phy_top/u_phy_read_top/nd_io_inst[1].u_phy_read_data_align/fall_data0<7>
on pin DIADI16 on location RAMB36_X5Y52
Conflict detected on wire: PINFEED(-90313,260920)
This issue only occurs when targeting a 576 Mb, -25 RLDRAMII device.
Solution
For this specific RLDRAMII device, the debug signals cannot be used in this release.
Please use the same design with the Debug Signals disabled to successfully implement the design.
This issue is scheduled to be resolved in MIG 3.4 released with ISE Design Suite 12.1.