When I implement the MIG output for a Virtex-6 FPGA RLDRAMII design with Debug Signals enabled, errors similar to the following occur during PAR:
This issue only occurs when targeting a 576 Mb, -25 RLDRAMII device.
For this specific RLDRAMII device, the debug signals cannot be used in this release.
Please use the same design with the Debug Signals disabled to successfully implement the design.
This issue is scheduled to be resolved in MIG 3.4 released with ISE Design Suite 12.1.