How do I use more than 4 output clocks when using the PPC440MC_DDR2 controller, for example a 5th clock for ECC support?
The number of output clocks is controlled by a MPD range constraint. Modifying the restriction should allow replication to any number of clock outputs. To modify the restriction:
1. Copy the ppc440mc_ddr2 core from the EDK install area to the local project pcore directory.
2. Open the ppc440mc_ddr2_v2_00_b\data\ppc440mc_ddr2_v2_1_0.mpd file.
3. Modify the RANGE setting of the C_NUM_CLK_PAIRS parameter to the desired maximum. For example, for five clocks modify the constraint to read:
PARAMETER C_NUM_CLK_PAIRS = 1, DT = integer, RANGE = (1:5), IO_IF = memory_0, IO_IS = C_MEM_CLK_WIDTH
4. Save and restart XPS.
5. Update the ppc440mc_ddr2 C_NUM_CLK_PAIRS parameter to the desired number of clock outputs.
The maximum will be increased to 5 starting with versions ppc440mc_ddr2_v2_00_d and newer, to be first released in EDK 11.4.