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AR# 33389

MIG v3.2, Virtex-6 FPGA DDR3 - ODT values incorrectly set for component-based design

Description

For MIG v3.2 Virtex-6 DDR3 component-based designs using on-die termination (ODT), MIG does not select the correct ODT values.  

In a component design, Rtt_nom should be set to the appropriate value (40, 60, or 120 ohms) based on the user system requirements (for example based on signal integrity simulation).

Dynamic ODT (Rtt_WR) should be disabled.

However, for a component design, the MIG GUI only gives the user the option of setting Rtt_WR, and automatically disables Rtt_nom.

Disabling Rtt_nom will cause ODT to be disabled during write-leveling.

This will adversely affect the signal integrity of the DQS nets and potentially affect the accuracy or completion of write-leveling.

Solution

To work around this issue, modify the following parameters at the topmost level of the MIG hierarchy to the following values:  

RTT_NOM = "40", "60", or "120" (depending on system requirements) 
RTT_WR = "OFF"
AR# 33389
Date Created 09/09/2009
Last Updated 08/14/2014
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG