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AR# 33391

11.3 Partial Reconfiguration Map - Long runtimes in placer phase x.10


When I run my design in the Partial Reconfiguration flow, it takes significantly longer than in the flat flow. In some runs, the runtime will increase by 35x or more. Why is this happening? Is there a way to speed up my runtimes?


This extra runtime is caused by specific algorithms within the placer. These algorithms are only intended to be called when previous placement algorithms fail, but there is a bug in the Partial Reconfiguration flow that is causing them to be called regardless of whether the previous algorithms found a solution.  


To speed up the placer in current software, contact Xilinx Technical Support to get further information on how to disable these algorithms.  




This will be fixed in a future version of software.

AR# 33391
Date 05/23/2014
Status Archive
Type General Article
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