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AR# 33402

MIG v3.2, Virtex-6 FPGA RLDRAMII - Data Mask signals are not properly propagated through the write path - RTL CHANGES REQUIRED


The MIG v3.2 Virtex-6 FPGA RLDRAMII design does not propagate the data mask (DM) signals from the user interface through the write path properly. Only the first device (device 0/dm0) has the data mask signal generated properly. All the others are tied low and not toggle if being used. Because of this, users might see unwanted data written to the first device while the other DM bits are always low. This is seen in both simulation and hardware.


To work around this issue, changes are required in the rld_phy_write_data_io.v module.

The following assign statements (starting on line 147) are incorrect: 

assign mux_dm_rise0 = (cal_done) ? wr_dm0[0] : init_wr_dm0[0]; 

assign mux_dm_fall0 = (cal_done) ? wr_dm0[1] : init_wr_dm0[1]; 

assign mux_dm_rise1 = (cal_done) ? wr_dm1[0] : init_wr_dm1[0]; 

assign mux_dm_fall1 = (cal_done) ? wr_dm1[1] : init_wr_dm1[1];

These assign statements need to be replaced with: 

assign mux_dm_rise0 = (cal_done) ? wr_dm0[NUM_DEVICES*2-1:NUM_DEVICES] :  


assign mux_dm_fall0 = (cal_done) ? wr_dm0[NUM_DEVICES-1:0] :  


assign mux_dm_rise1 = (cal_done) ? wr_dm1[NUM_DEVICES*2-1:NUM_DEVICES] :  


assign mux_dm_fall1 = (cal_done) ? wr_dm1[NUM_DEVICES-1:0] :  


AR# 33402
Date 05/23/2014
Status Archive
Type General Article
  • Virtex-6 CXT
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