Description

 # ** Warning: (vsim-3015) sim_tb_top.v(608): [PCDPC] - Port size (1 or 1) does not match connection size (2) for port 'cs_n'. 

 # ** Warning: (vsim-3015) sim_tb_top.v(608): [PCDPC] - Port size (1 or 1) does not match connection size (2) for port 'odt'

Solution

These warnings occur because of signal port width mismatches in the sim_tb_top.v testbench module. 

For UDIMM designs, the CS and ODT signal widths are 2. 

However, in the testbench (sim_tb_top.v) only 1 bit is port mapped to the memory model instance.

To work around these warnings, replace the following code in the sim_tb_top.v module: 

Original Code 

.cs_n (ddr2_cs_n_sdram), 
.odt (ddr2_odt_sdram)

.cs_n (ddr2_cs_n_sdram[i/8]), 
.odt (ddr2_odt_sdram[i/8])