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AR# 33411

Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - After warm reset, TX direction stalls forever because of deassertion of trn_tdst_rdy_n


Known Issue: v1.12, v1.11, v1.10.1, v1.10, v1.9.4

A problem has been found where, after a warm reset, the Block Plus wrapper transmit direction occasionally stalls forever by deasserting trn_tdst_rdy_n.


This problem only happens after a warm reset and does not happen on a power cycle. Once it locks up, a power cycle is required to clear the problem. The core deasserts trn_tdst_rdy_n forever. The issue seems to be rare and does not happen every time a warm reset is issued. The problem is also related to initial credits advertised by the link partner, so it may not occur on all systems.

In v1.12 and later, the wrapper source files are now delivered with the generated core. Place the pcie_blk_ll_credit.v file found in the zip below in the directory: <generated_core_name>/source

If you are using the v1.11 core, you will need to place the file into the folder:


or a similar path for your installation.

Regenerate the v1.11 core from CORE Generator.

The zip containing the workaround is here:


Note that this zip file contains workarounds for other issues in v1.12. Please see the readme.txt in the zip file for more information.

This workaround file should not be used on cores prior to v1.11.

These fixes will be included in the v1.13 Block Plus Core included in ISE Design Suite11.4.

Revision History
07/05/2011 - Updated title
10/26/2009 - Added workaround file.
09/22/2009 - Updated for ISE 11.3 and v1.12 core release
09/08/2009 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33580 Design Advisory for the Virtex-5 FPGA Endpoint Block Plus Wrapper for PCI Express Master Answer Record N/A N/A

Associated Answer Records

AR# 33411
Date 05/22/2012
Status Active
Type Design Advisory
  • Virtex-5 Integrated Endpoint Block
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