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AR# 33415: MIG v3.2, Virtex-6 FPGA DDR2DDR3 - Master Bank selection is not enabled in some cases which require a Master Bank
MIG v3.2, Virtex-6 FPGA DDR2DDR3 - Master Bank selection is not enabled in some cases which require a Master Bank
MIG v3.2 does not enable the Master Bank selection box for specific Virtex-6 FPGA DDR2/DDR3 designs even though a Master Bank is required.
The tools allow the design to generate, but the following error occurs during MAP:
ERROR:Place:899 - The following IOBs use the Digitally Controlled Impedance feature (DCI) and have been locked (LOC constraint) to the I/O bank 33. This feature requires the VRN and VRP pins within the same I/O bank to be connected to reference resistors. The following VR pins are currently locked and cannot be used to supply the necessary reference.
IO Standard: Name = DIFF_SSTL15_T_DCI, VREF = NR, VCCO = 1.50, TERM = SPLIT, DIR = BIDIR, DRIVE_STR = NR
List of locked IOB's:
List of occupied VR Sites:
VR site IOB_X2Y55 is occupied by comp phy_init_done
This issue arises when VRN/VRP pins are used in a bank by Address/Control or System Control groups.
To work around this issue, manually add the DCI Cascade syntax in the generated UCF file: