AR# 33439


MIG v3.2, Virtex-6 FPGA DDR2/DDR3 - ECC not supported for data widths equal to 120-bit


The MIG v3.2 Virtex-6 FPGA DDR2/DDR3 design has an issue with the H-Matrix generated by the ECC code for data widths equal to 120-bits.

Therefore, this configuration cannot support ECC with the MIG v3.2 release.


This issue is resolved in MIG v3.3, available with ISE Design Suite 11.4.
AR# 33439
Date 08/14/2014
Status Active
Type General Article
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