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MIG v3.2-3.61 Virtex-6 DDR2 - When ODT is disabled (RTT_NOM = 0), ODT is incorrectly asserted immediately following calibration
When ODT is disabled (RTT_NOM), the ODT pin is expected to be held LOW until an EMRS command is applied to enable ODT.
The MIG Virtex-6 FPGA DDR2 design incorrectly asserts the ODT signal after the design completes calibration.
Because the controller programmed the memory with ODT disabled, the memory ignores the ODT toggling.
This does not cause any issues in simulation or hardware.
This can be fixed by opening sim_tb_top.v/vhd, example_design.v/vhd, and the User Design top-level <your_design_name>.v/vhd and setting RTT_NOM="DISABLED".
This issue is fixed in the ISE 13.1 MIG v3.7 software release.
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- Virtex-6 CXT
- Virtex-6 HXT
- Virtex-6 LX
- Virtex-6 LXT
- Virtex-6 SXT