AR# 33440

MIG v3.2-3.61 Virtex-6 DDR2 - When ODT is disabled (RTT_NOM = 0), ODT is incorrectly asserted immediately following calibration


When ODT is disabled (RTT_NOM), the ODT pin is expected to be held LOW until an EMRS command is applied to enable ODT.

The MIG Virtex-6 FPGA DDR2 design incorrectly asserts the ODT signal after the design completes calibration.


Because the controller programmed the memory with ODT disabled, the memory ignores the ODT toggling.

This does not cause any issues in simulation or hardware.

This can be fixed by opening sim_tb_top.v/vhd, example_design.v/vhd, and the User Design top-level <your_design_name>.v/vhd and setting RTT_NOM="DISABLED".

This issue is fixed in the ISE 13.1 MIG v3.7 software release.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
38951 MIG v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4-14.2 N/A N/A
AR# 33440
Date 08/14/2014
Status Active
Type General Article
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