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MIG v3.2, v3.3, Virtex-6 FPGA DDR2/DDR3 - Periodic reads associated with the phase detector are not properly sent according to the tPRDI timing parameter
The MIG v3.2/v3.2 DDR2/DDR3 design issues periodic reads as a part of the phase detector circuit to maintain the data capture window over VT variations.
The tPRDI parameter defines the time period between the periodic reads.
During idle bus time, the time period defined by this parameter ensures that a read is sent to monitor DQS and performs any adjustment needed.
Please see the Virtex-6 FPGA Memory Interface Solutions User Guide (UG406) for full details.
In some cases, this read is not sent according to the tPRDI parameter.
This issue occurs in cases where the tREFI period is greater than the tPRDI period.
This has minimal effect as the periodic read is sent approximately 30 clock cycles later, allowing the phase detection to complete.
This issue is resolved in MIG v3.4, which was released with ISE Design Suite 12.1.
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