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MIG v3.2, Virtex-6 FPGA DDR2/DDR3 - Read associated with Read Modified Write command is incorrectly issued as a Read with Auto-Precharge
The MIG v3.2 Virtex-6 FPGA DDR2/DDR3 designs support Read Modified Write commands.
However, in some cases the Read associated with the Read Modify Write command is issued as a Read with Auto-Precharge.
This causes the bank to close and so when the controller issues the associated Write to the same location, there is no Activate command and as a result the Write cannot complete.
This issue does not always occur, but has been seen when ORDERING is set to NORM and RELAXED as well as when ECC is used for partial byte enables.
This issue will be resolved in MIG v3.3 which will be released with IDS 11.4.
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