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AR# 33453

Serial RapidIO v5.4 - VHDL example design simulation error with core_clk.vhd


When simulating a Virtex-6 FPGA RapidIO v5.4 core, with x1 lane width and 1.25G line rate, the VHDL simulation produces the following error:

"../../example_design/core_clk.vhd(131): Integer literal 13 is not of type std.standard.real."


To work around this issue, change the CLKOUT0_DIVIDE_F attribute value of the MMCM from "13" to "13.0"

This issue will be fixed in the next core release.

Revision History

09/16/2009 - Initial Release

AR# 33453
Date 12/15/2012
Status Active
Type General Article
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