There have been reports of 2 designs implemented in the Virtex-4 and Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC blocks erroneously appending the end of some transmitted frames with an additional byte. This byte is a duplication of the final byte of the FCS.
If this rare issue is encountered, erroneous operation may not be consistent across multiple devices or bitstreams, may not be consistent between power or reset cycles for a given combination of device and bitstream, and will not affect every transmitted frame.
This issue is limited to the following Ethernet MAC configurations:
- Configurations using the MII physical interface
- 10 or 100 Mbps operation when using the RGMII physical interface
- 10 or 100 Mbps operation when using the Tri-speed GMII physical interface (Byte PHY clocking scheme excluded)
The following solution should be used with the LogiCORE IP Embedded Tri-Mode Ethernet MAC Wrapper (Virtex-4 FX family) v4.7 and earlier, and the LogiCORE IP Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper v1.6 and earlier.
Xilinx has developed logic which can be integrated into the Virtex-4 or Virtex-5 FPGA Ethernet MAC wrapper to correct the erroneous behavior. It resides on the PHY-side transmit path, and checks each frame for duplication of the final FCS byte. If duplication occurs, it corrects the transmit enable signaling to exclude the duplicated byte from the frame.
HDL source code, examples, and further instructions can be downloaded from the following link:
This solution is scheduled to be integrated into the next release of the LogiCORE IP Embedded Tri-mode Ethernet MAC Wrappers for Virtex-4 and Virtex-5 devices.