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AR# 33486

LogiCORE XAUI v9.1 and RXAUI v1.1 - Update needed for reset logic in block level for Spartan-6 Device GTP and Virtex-6 Device GTX wrappers

Description

For Spartan-6 FPGA and Virtex-6 FPGA designs, the transceiver PCS resets should be asserted when reset156 is asserted to ensure that the PCS is held in reset until all clocks are valid.

Solution

The reset logic can be updated by making the following changes to the "example_design/<core_name>_block.v/vhd" file. 

 

If using VHDL 

 

1. Change:  

mgt_txreset <= not lock;  

To: 

mgt_txreset <= reset156; 

 

2. Add:  

signal cbm_rx_reset : std_logic; 

 

3. Change the reset output on the channel bonding monitor to a new signal name.  

Change: 

RXRESET => mgt_rx_reset 

To: 

RXRESET => cbm_rx_reset 

 

4. Drive mgt_rx_reset with both the reset from the channel bonding monitor block and the reset156: 

 

mgt_rx_reset <= cbm_rx_reset or reset156; 

 

5. If using the Virtex-6 64-bit internal interface in "example_design/<core_name>_example_design.vhd": 

Change: 

reset_156_r1 <= '0'; 

To: 

reset_156_r1 <= not txlock; 

 

If using Verilog 

 

1. Change:  

assign mgt_txreset = ~lock; 

To: 

assign mgt_txreset = reset156; 

 

2. Add:  

wire cbm_rx_reset; 

 

3. Change the reset output on the channel bonding monitor to a new signal name.  

Change: 

.RXRESET(mgt_rx_reset) 

To: 

.RXRESET(cbm_rx_reset) 

 

4. Drive mgt_rx_reset with both the reset from the channel bonding monitor block and the reset156: 

 

assign mgt_rx_reset = cbm_rx_reset | reset156; 

 

5. If using the Virtex-6 64-bit internal interface in "example_design/<core_name>_example_design.v": 

Change: 

reset156_r1 <= 1'b0; 

To: 

reset_156_r1 <= ~txlock;

Linked Answer Records

Associated Answer Records

AR# 33486
Date Created 09/11/2009
Last Updated 12/01/2014
Status Active
Type General Article
Devices
  • Spartan-6
  • Virtex-6