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AR# 33530

LogiCORE IP v1.3 CIC Compiler - Why is the output of my CIC Compiler block always undefined X's in HDL Simulation or NAN's in System Generator?

Description

Keywords: sysgen, unkown, nothing, SysGen

Why is the output of my CIC Compiler block always undefined X's in HDL Simulation or NAN's in System Generator?

Solution

The architecture of a CIC filter uses feedback. As a result, if an undefined input such as an X (HDL simulation) or NAN (System Generator) is input to the DIN port, the output will remain unknown until the core is reset.
AR# 33530
Date Created 09/17/2009
Last Updated 09/17/2009
Status Active
Type General Article